RTL design & verification
Write Verilog/SystemVerilog and testbenches that pass simulation and synthesis checks.
20 project-authored proposals · taxonomy v1.1 · 0 new benchmark runs. Verifiers and partial-credit rules below are designs, not executed results.
- Typical applications
- Icarus Verilog · Verilator · Yosys · Vivado
- Class GUI-need label
CL· CLI-sufficient
Task proposals · 20
Expand to inspect the complete original wording and proposed checks. Original proposal text remains English in both interfaces.
R02.06.01.02-T01 Implement a parameterized synchronous FIFO with almost-full flags
Original instruction
Write rtl/sync_fifo.sv: parameters WIDTH and DEPTH (power of two), single clock, active-low synchronous reset, push/pop with full, empty, almost_full (DEPTH-2) and almost_empty (2) flags, and a count output. Simultaneous push and pop when full must pop and push in the same cycle.
- Platforms
lin· Linuxmac· macOS- Applications
- Icarus Verilog · Verilator
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Hidden testbench (Icarus and Verilator, 3 parameter sets) runs 20k random push/pop cycles against a Python reference model via cocotb: zero mismatches on data and flags. Verilator --lint-only -Wall clean.
Proposed partial credit
50% data ordering; 30% flags and count; 10% full push+pop; 10% lint clean
R02.06.01.02-T02 Build a UART transmitter and receiver with 16x oversampling
Original instruction
Implement rtl/uart.sv with a parameterized clock and baud (default 50 MHz, 115200), 8N1, 16x oversampled RX with mid-bit sampling and framing-error flag, and a TX with busy signal. Provide a cocotb test in tb/test_uart.py covering back-to-back bytes.
- Platforms
lin· Linuxmac· macOS- Applications
- Icarus Verilog · cocotb
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Hidden cocotb suite: loopback of 1,000 random bytes at 3 baud rates; RX tolerates ±2% baud mismatch; framing error asserted on bad stop bit; TX bit period within 1 clock of ideal. Agent's own test must pass.
Proposed partial credit
30% TX timing; 40% RX with baud tolerance; 15% framing error; 15% agent test passes
R02.06.01.02-T03 Find and fix an AXI4-Lite handshake bug from a failing waveform
Original instruction
rtl/axil_regs.sv fails the provided tb/axil_tb.sv: writes occasionally drop when AWVALID and WVALID arrive in different cycles. Read sim/fail.vcd, fix the slave so it accepts address and data in any order without deadlock, and keep register map behavior.
- Platforms
lin· Linuxmac· macOS- Applications
- Icarus Verilog · GTKWave
- Interfaces
term· Terminaldesk· Desktop GUI- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commandsvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Hidden AXI-Lite VIP (cocotbext-axi) runs 5k randomized transactions with independent AW/W/B/AR/R backpressure: zero lost writes, no protocol-check violations, registers read back correctly. Diff limited to axil_regs.sv.
Proposed partial credit
50% randomized transactions pass; 30% protocol checker clean; 20% register map unchanged
R02.06.01.02-T04 Prove a round-robin arbiter's fairness with SystemVerilog assertions
Original instruction
For rtl/rr_arbiter.sv (4 requesters), write formal/rr_props.sv with assertions for one-hot grant, grant only to requesters, and starvation-freedom (a held request is granted within 4 cycles). Prove them with SymbiYosys and fix any bug the proof finds.
- Platforms
lin· Linux- Applications
- SymbiYosys · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader runs sby on agent properties: all PASS in prove mode. Hidden property set (including a liveness bound) is also proven against the fixed RTL. Mutation check: properties must fail on 4 seeded buggy arbiter variants.
Proposed partial credit
30% agent properties proven; 30% hidden properties pass; 40% mutation kill rate (4 variants)
R02.06.01.02-T05 Design an asynchronous FIFO with Gray-code pointers
Original instruction
Implement rtl/async_fifo.sv (WIDTH, DEPTH=2^N) with independent write and read clocks, Gray-coded pointers, two-flop synchronizers and correct full/empty generation. Simulate with unrelated clock ratios and check CDC structure.
- Platforms
lin· Linuxmac· macOS- Applications
- Verilator · Icarus Verilog · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Hidden cocotb test with 6 clock ratios (incl. 1:7 and 7:1) and random enables: no data loss/duplication over 50k words; full/empty never false-negative. Yosys-based structural check: every crossing goes through a 2-flop synchronizer of Gray-coded pointers.
Proposed partial credit
50% data integrity across ratios; 20% flag correctness; 30% CDC structure check
R02.06.01.02-T06 Write a self-checking ALU testbench that catches seeded bugs
Original instruction
Write tb/alu_tb.sv with constrained-random stimulus, a reference model and functional coverage for rtl/alu.sv (16 ops, flags). The testbench must pass on the golden ALU and report coverage of all ops × flag outcomes.
- Platforms
lin· Linuxmac· macOS- Applications
- Icarus Verilog · Verilator
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader runs the testbench against the golden ALU (must pass, coverage report lists 100% op×flag bins) and 12 hidden mutants (must fail on ≥11). Runtime ≤60 s per run.
Proposed partial credit
20% passes on golden; 20% coverage complete; 60% mutants detected (5 pts each)
R02.06.01.02-T07 Fit a design into an iCE40 LUT budget at 48 MHz
Original instruction
rtl/pixel_pipe.v synthesizes to 910 LUTs on iCE40UP5K and closes at 31 MHz. Reduce it to ≤600 LUTs and Fmax ≥48 MHz with Yosys and nextpnr-ice40 while staying cycle-accurate to the original at the ports, except for added pipeline latency documented in output/latency.txt.
- Platforms
lin· Linuxmac· macOS- Applications
- Yosys · nextpnr
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader runs yosys synth_ice40 + nextpnr (fixed seed): LUT count ≤600, Fmax ≥48 MHz. Hidden testbench compares output streams with the original shifted by the declared latency: identical for 100k pixels.
Proposed partial credit
35% LUT target; 35% Fmax target; 30% functional equivalence with declared latency
R02.06.01.02-T08 Close timing on an Artix-7 design in Vivado
Original instruction
Vivado project fixtures/fir_a7 (xc7a35t, 200 MHz clock) has WNS of -1.8 ns. Use the timing report and schematic views to find the critical paths, add pipelining or retiming, and re-implement until WNS ≥0 with no hold violations. Save the timing summary to output/timing.rpt.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickvis· Visual judgmentcode· Code & commands- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Grader re-runs synth+impl in batch from the agent's project: WNS ≥0, WHS ≥0, no unconstrained paths, no timing-relaxing constraints added (XDC diff limited to original). Behavioral testbench vs reference FIR output identical after latency alignment.
Proposed partial credit
40% WNS ≥0; 15% hold clean; 15% no constraint cheating; 30% functional equivalence
R02.06.01.02-T09 Implement a vending-machine FSM from a written spec
Original instruction
Implement rtl/vend_fsm.sv from spec/vending.md: coins 5/10/25, item price 35, change returned in fewest coins, cancel returns inserted total. Use an enumerated-state Moore machine.
- Platforms
lin· Linuxmac· macOS- Applications
- Icarus Verilog
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Hidden testbench runs all coin sequences up to length 6 plus cancels against a Python model: outputs identical every cycle. Verilator lint clean; states declared as enum.
Proposed partial credit
70% sequence equivalence; 20% change minimal; 10% lint and enum
R02.06.01.02-T10 Clean a legacy core of all Verilator lint warnings
Original instruction
Make rtl/legacy_dsp/ (11 Verilog files) pass 'verilator --lint-only -Wall' with zero warnings and no lint_off pragmas, without changing behavior.
- Platforms
lin· Linuxmac· macOS- Applications
- Verilator · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Grader runs Verilator -Wall: zero warnings; grep rejects lint_off and waiver files. Yosys equiv_make/equiv_simple + equiv_induct between original and edited design proves equivalence for all modules.
Proposed partial credit
50% zero warnings; 10% no pragmas; 40% formal equivalence
R02.06.01.02-T11 Add forwarding and stall logic to a 5-stage RV32I pipeline
Original instruction
rtl/rv32i_core/ is a 5-stage pipeline with no hazard handling. Add EX/MEM and MEM/WB forwarding, load-use stalls and branch flushes so riscv-tests rv32ui pass, then report CPI on the provided CoreMark build.
- Platforms
lin· Linux- Applications
- Verilator · riscv-gnu-toolchain
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Grader runs all 39 rv32ui-p tests in Verilator: pass count. CoreMark run completes with a valid checksum and CPI ≤1.35 (no forwarding baseline 1.9). output/cpi.txt within 1% of measured.
Proposed partial credit
60% rv32ui pass rate; 25% CoreMark CPI target; 15% CPI reported correctly
R02.06.01.02-T12 Write an SPI master supporting all four modes
Original instruction
Implement rtl/spi_master.sv with CPOL/CPHA mode select, configurable clock divider, 8–32-bit transfers, and chip-select hold. Verify against the provided SPI slave model in tb/.
- Platforms
lin· Linuxmac· macOS- Applications
- Icarus Verilog · cocotb
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Hidden cocotb test: for each of 4 modes and 3 widths, 200 random transfers to the slave model; MOSI/MISO data exact and SCLK edges match mode timing (sample/shift edges). CS stays low for the whole transfer.
Proposed partial credit
60% data across modes; 25% edge timing; 15% CS behavior
R02.06.01.02-T13 Implement a 16-tap fixed-point FIR matching a Python golden model
Original instruction
Implement rtl/fir16.sv: Q1.15 input, coefficients from data/coeffs.txt, full-precision accumulation, rounding to Q1.15 with saturation, one sample per clock throughput. Match the golden outputs from model/fir_golden.py.
- Platforms
lin· Linuxmac· macOS- Applications
- Verilator · Python
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader feeds 3 hidden stimulus files (impulse, chirp, full-scale noise): outputs within ±1 LSB of golden for all samples, saturation exact on overflow cases; throughput 1 sample/clk after latency.
Proposed partial credit
20% impulse response; 50% chirp+noise within 1 LSB; 20% saturation; 10% throughput
R02.06.01.02-T14 Translate a VHDL CRC module to SystemVerilog with equivalence
Original instruction
Translate rtl/vhdl/crc32_stream.vhd into rtl/crc32_stream.sv preserving ports, reset behavior and latency, using idiomatic SystemVerilog. Show equivalence with the original.
- Platforms
lin· Linux- Applications
- Yosys · GHDL · Icarus Verilog
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader uses Yosys + ghdl-yosys-plugin equivalence checking (equiv_induct) on both designs: proven equivalent. Also 10k random-stream co-simulation identical. File contains no VHDL-isms (lint).
Proposed partial credit
60% formal equivalence; 30% co-simulation; 10% lint clean
R02.06.01.02-T15 Pinpoint the first divergence in two waveforms
Original instruction
sim/golden.vcd and sim/dut.vcd come from the same test on two revisions of a DMA engine. Using a waveform viewer (GTKWave or Surfer), find the first clock cycle where any top-level output differs, the signal, and the internal register that caused it. Write output/divergence.json with {cycle, signal, root_cause_signal}.
- Platforms
lin· Linuxmac· macOSwin· Windows- Applications
- GTKWave · Surfer
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
vis· Visual judgmentnav· Pan/zoom/scroll- Work product
WP12· Answer/decision- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Exact match on cycle and signal; root_cause_signal must equal the seeded bug register. A VCD-diff script could find the cycle, so the root-cause field (requires tracing internal fan-in) carries most weight.
Proposed partial credit
30% cycle; 20% output signal; 50% root-cause register
R02.06.01.02-T16 Assemble a Zynq block design with AXI GPIO and UART Lite
Original instruction
In Vivado IP Integrator, create a block design for the Zynq-7020 board fixture: PS7 with DDR and FIXED_IO, AXI GPIO (8 LEDs, 4 switches), AXI UART Lite at 115200, address map per input/addrmap.csv, run Validate Design, generate the wrapper and bitstream, and export the XSA.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropclick· Point & click- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Grader opens the .bd via vivado -mode batch: required IP present with parameters, interconnect connections, address segments exactly as CSV; validate_bd_design clean; bitstream and XSA exist with matching hash of the hardware handoff.
Proposed partial credit
30% IP and parameters; 30% connections; 25% address map; 15% bitstream/XSA
R02.06.01.02-T17 Add pulse and handshake synchronizers across clock domains
Original instruction
rtl/ctrl_top.sv passes single-cycle pulses and a 16-bit config bus from a 100 MHz domain to a 27 MHz domain unsynchronized. Add a toggle-based pulse synchronizer and a req/ack handshake for the bus, keeping the interface unchanged.
- Platforms
lin· Linuxmac· macOS- Applications
- Verilator · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Hidden simulation with jittered clocks: every pulse arrives exactly once, bus values never torn (checked at each ack). Structural CDC script finds no unsynchronized crossings.
Proposed partial credit
40% pulse delivery; 40% bus integrity; 20% structural CDC clean
R02.06.01.02-T18 Reach full functional coverage on a packet parser with cocotb
Original instruction
Write a cocotb testbench (tb/test_parser.py) with constrained-random packets, a scoreboard and cocotb-coverage bins for rtl/pkt_parser.sv (Ethernet/VLAN/IPv4/IPv6/UDP/TCP combinations, bad checksums, truncated frames). Reach 100% of the bins defined in spec/coverage_plan.md.
- Platforms
lin· Linux- Applications
- cocotb · Verilator
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader runs the testbench: coverage XML must hit 100% of the plan's 64 bins; passes on golden RTL; fails on ≥5 of 6 hidden mutants; runtime ≤5 min.
Proposed partial credit
40% coverage; 20% passes golden; 40% mutant detection
R02.06.01.02-T19 Cut flip-flop count by 30% without changing behavior
Original instruction
rtl/stats_unit.sv uses 1,240 flip-flops. Reduce it to ≤870 while keeping cycle-accurate port behavior, by sharing registers and removing redundant pipeline state.
- Platforms
lin· Linux- Applications
- Yosys · SymbiYosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Yosys stat after synth: DFF count ≤870. Sequential equivalence proven with a SymbiYosys miter (bounded 40 cycles + induction) between original and new design.
Proposed partial credit
50% DFF target (linear credit from 1,240); 50% equivalence proof
R02.06.01.02-T20 Fix an SDRAM controller's refresh timing violation
Original instruction
rtl/sdram_ctrl/ fails long simulations with the Micron MT48LC16M16 model reporting tRFC and refresh-interval violations under heavy traffic. Diagnose with the model warnings and waveforms, fix refresh scheduling and command timing, and sustain ≥80% bus utilization.
- Platforms
lin· Linuxmac· macOS- Applications
- Icarus Verilog · GTKWave
- Interfaces
term· Terminaldesk· Desktop GUI- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commandsvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Grader runs a hidden 20 ms traffic simulation with the vendor model: zero timing warnings (tRFC, tRP, tRCD, 8192 refreshes/64 ms), data integrity on all reads, utilization ≥80% computed from command trace.
Proposed partial credit
40% no timing violations; 30% data integrity; 30% utilization target
Mapped research references
Existing benchmark-to-class links from the research catalog. They are not record-level annotations, executions or product endorsements.