Schematic capture & ERC
Enter schematics with correct symbols, nets and annotations that pass ERC.
20 project-authored proposals · taxonomy v1.1 · 0 new benchmark runs. Verifiers and partial-credit rules below are designs, not executed results.
- Typical applications
- KiCad · Altium Designer · OrCAD
- Class GUI-need label
G2· GUI-essential
Task proposals · 20
Expand to inspect the complete original wording and proposed checks. Original proposal text remains English in both interfaces.
R07.03.01.01-T01 KiCad: ATmega328P minimal system schematic with ERC clean
Original instruction
In KiCad 8 Schematic Editor, create output/mcu_min.kicad_sch per input/mcu_spec.pdf: ATmega328P-AU, 16 MHz crystal with 22 pF caps, 100 nF decoupling on each VCC/AVCC pin, 10 µF bulk, 10 k reset pull-up, 2×3 ISP header, power LED. Annotate and run ERC.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader runs kicad-cli sch erc (0 errors, 0 warnings except allowed list) and exports a netlist; netlist graph isomorphic to reference (part values/pin-to-net mapping). The agent VM has no shell, text editor or Python (no SKiDL) and KiCad's IPC API is disabled; schematics not saved by Eeschema are flagged.
Proposed partial credit
25% all parts with values; 45% netlist isomorphism; 20% ERC clean; 10% annotation.
R07.03.01.01-T02 Altium: net labels and ports so a three-sheet design compiles
Original instruction
Open input/sensor_hub.PrjPcb (3 sheets: power, MCU, sensors). Add net labels, power ports and sheet entries/ports so the project compiles with no 'Floating net label', 'Unconnected pin' or 'Nets with only one pin' errors, matching the intended connectivity in input/netlist_intent.csv.
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Grader compiles via Altium's command-line validation (read-only) and exports a netlist: listed error classes = 0; net membership matches intent CSV (pin-level F1 = 1.0 for full credit). Altium's scripting system (DelphiScript/VBScript) is disabled for the agent, and a file-system audit log flags .SchDoc/.PrjPcb writes not made by Altium Designer.
Proposed partial credit
40% compile errors cleared; 60% connectivity matches intent.
R07.03.01.01-T03 KiCad: add decoupling capacitors to every IC power pin
Original instruction
In input/logic_board.kicad_sch, add a 100 nF 0402 capacitor between each VCC pin and GND for all three ICs (U1–U3, 7 power pins total), annotate them C10–C16, assign footprint Capacitor_SMD:C_0402_1005Metric, and keep ERC clean.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Netlist: 7 new caps each connected between a distinct IC VCC pin net and GND; references C10–C16; footprint field exact; ERC 0 errors. The agent VM has no shell, text editor or Python and KiCad's IPC API is disabled, so .kicad_sch files can only change by saving from Eeschema.
Proposed partial credit
50% seven caps correctly connected; 20% references; 20% footprints; 10% ERC.
R07.03.01.01-T04 OrCAD Capture: hierarchical four-channel ADC front-end
Original instruction
In OrCAD Capture, create a hierarchical block 'AFE_CH' (input protection, op-amp buffer, RC anti-alias per input/afe.pdf) and instantiate it 4 times on the top sheet feeding ADC inputs AIN0–AIN3, with unique net names per channel. Annotate and run DRC.
- Platforms
win· Windows- Applications
- OrCAD Capture
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Exported netlist: 4 instances of the channel subcircuit (occurrence-based references unique), each wired to its AIN net; subcircuit topology matches reference; Capture DRC report no errors. Capture's Tcl command window and script autoload are disabled for the agent and its VM has no shell, so the design must be drawn in Capture.
Proposed partial credit
30% hierarchical block correct; 30% four instances wired; 20% unique occurrence annotation; 20% DRC clean.
R07.03.01.01-T05 KiCad: USB-C power sink with CC resistors and ESD protection
Original instruction
Draw output/usbc_sink.kicad_sch: USB-C receptacle (16-pin), 5.1 kΩ pull-downs on CC1/CC2, TVS on VBUS, ESD array on D+/D−, polyfuse, and 3.3 V LDO with input/output caps per input/usbc_spec.pdf. ERC clean.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Netlist isomorphism vs reference; check rules: each CC has its own 5.1 k to GND (not shared), both D+ and D− pins on the receptacle tied pairwise; ERC 0 errors. The agent VM has no shell, text editor or Python and KiCad's IPC API is disabled, so .kicad_sch files can only change by saving from Eeschema.
Proposed partial credit
30% CC network; 30% protection parts; 20% LDO; 20% ERC.
R07.03.01.01-T06 KiCad Symbol Editor: 48-pin MCU symbol from a datasheet pin table
Original instruction
Create symbol 'XM48' in project library output/xm.kicad_sym from input/xm48_pinout.pdf: all 48 pins with exact numbers, names and electrical types (power in, I/O, passive, NC), grouped by function on the four sides, then place it in a test schematic and pass ERC.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Parsed .kicad_sym: 48 pins, number→name map exact, electrical types exact; pins on 100 mil grid; no overlapping pins. File must be saved by the Symbol Editor (format/ordering signature); generated symbol files flagged.
Proposed partial credit
40% number/name map; 30% electrical types; 20% grid and layout; 10% ERC test.
R07.03.01.01-T07 Altium: assembly variant with DNP parts and per-variant BOM
Original instruction
In input/sensor_hub.PrjPcb, create variant 'Lite' with U5, U6, J4, R20–R22 not fitted and C30 alternate value 4.7 µF, then generate BOMs for 'Full' and 'Lite' to output/bom_full.csv and output/bom_lite.csv.
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & forms- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Project file variant definitions exactly as specified; BOM CSVs equal reference (designators, values, quantities). Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the project must be edited in the Altium GUI.
Proposed partial credit
40% variant definitions; 30% Lite BOM; 30% Full BOM.
R07.03.01.01-T08 EasyEDA: recapture a legacy scanned schematic
Original instruction
In EasyEDA Pro (web, sandbox account), redraw the 40-part analog board from input/legacy_scan.png (a scanned hand-drawn schematic) using library parts with the shown values, then export the netlist.
- Platforms
web· Any OS (web)- Applications
- EasyEDA Pro
- Interfaces
brow· Browser- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickdrag· Drag & dropvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Exported netlist vs ground-truth netlist: graph isomorphism score (pin-level F1) and value accuracy; ERC clean. Image is hand-drawn so values require reading the scan. EasyEDA Pro extensions and API are disabled for the agent's account and netlist/JSON import is withheld, so the schematic must be drawn in the editor.
Proposed partial credit
60% connectivity F1; 25% values; 15% ERC clean.
R07.03.01.01-T09 KiCad: clear twelve ERC errors without changing intended connectivity
Original instruction
input/sensor_node.kicad_sch has 12 ERC errors (missing power flags, wrong pin types on a custom symbol, dangling wires, label typos 'SDA' vs 'SDA_'). Fix all so ERC reports 0 errors and the netlist equals input/intended.net.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickvis· Visual judgmenttype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
kicad-cli ERC: 0 errors; exported netlist equals intended.net; suppressing ERC rules or excluding violations scores 0 for those items (ERC settings diff checked). The agent VM has no shell, text editor or Python and KiCad's IPC API is disabled, so .kicad_sch files can only change by saving from Eeschema.
Proposed partial credit
50% ERC errors fixed without exclusions; 50% netlist equals intent.
R07.03.01.01-T10 Altium: 16-bit data bus with bus entries and harness
Original instruction
In input/memif.SchDoc, connect the MCU's D0–D15 to the SRAM and the level shifter using a bus 'D[0..15]' with bus entries and net labels, and route the control signals (CS, OE, WE) as a signal harness to the second sheet.
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & dropgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Compiled netlist: D0–D15 connect exactly MCU↔SRAM↔shifter pins per pin map; harness definition file contains CS/OE/WE and they reach sheet 2 nets; no compile errors. Altium's scripting system (DelphiScript/JScript) is disabled for the agent, and a file-write audit fails any SchDoc not saved by the Altium UI process.
Proposed partial credit
50% bus connectivity; 30% harness; 20% compile clean.
R07.03.01.01-T11 KiCad: quad op-amp units across three filters
Original instruction
Place an LM324 (multi-unit symbol) and use units A–C for the three active filters in input/filters.kicad_sch per input/filters.pdf, unit D as a grounded follower, and the power unit tied to ±12 V. Annotate as U1A–U1D.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Netlist: one package U1 with units mapped as specified; unused unit D as follower to GND; power pins on ±12 V; values of filter components exact. The agent VM has no shell, text editor or Python and KiCad's IPC API is disabled, so .kicad_sch files can only change by saving from Eeschema.
Proposed partial credit
40% unit assignment; 20% power unit; 30% filter values; 10% annotation.
R07.03.01.01-T12 OrCAD: heterogeneous multi-section part with PSpice model link
Original instruction
In OrCAD Capture, create part 'REL_SPDT' with two heterogeneous sections (coil, contact) in a project library, add PSPICETEMPLATE and IMPLEMENTATION properties linking to input/relay.lib, place it in input/driver.dsn, and run PSpice netlist generation.
- Platforms
win· Windows- Applications
- OrCAD Capture · PSpice
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & forms- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Library part has 2 heterogeneous sections with pin numbers per spec; properties exact; PSpice netlist generation succeeds and contains the subcircuit call with correct node order. Capture's Tcl command window and script autoload are disabled for the agent and its VM has no shell, so the design must be drawn in Capture.
Proposed partial credit
40% part sections; 30% properties; 30% netlist generation.
R07.03.01.01-T13 KiCad: assign footprints from a mapping table with the assignment tool
Original instruction
In input/ctrl.kicad_sch (42 parts), assign footprints per input/footprints.csv (by reference or value/package) using KiCad's Footprint Assignment tool, and save.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Every symbol's Footprint field equals the CSV mapping; no unassigned footprints; file saved by KiCad (format signature).
Proposed partial credit
50% parts 1-21 footprints match CSV (pro rata); 50% parts 22-42 match (pro rata).
R07.03.01.01-T14 Altium: reuse a device sheet and integrate it
Original instruction
Insert device sheet 'BuckConverter_5V' from the managed library into input/sensor_hub.PrjPcb as a sheet symbol, connect VIN, 5V and GND ports to the top sheet, make the device sheet's references unique within the project, and compile cleanly.
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Project contains the device sheet; ports connected to correct nets; designators unique; compile with no errors. Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the project must be edited in the Altium GUI.
Proposed partial credit
30% device sheet inserted; 40% ports connected; 30% clean compile and unique designators.
R07.03.01.01-T15 KiCad: eight identical hierarchical channels with unique nets
Original instruction
Create a hierarchical sheet 'chan.kicad_sch' (LED driver channel per input/chan.pdf) and instantiate it 8 times from the root sheet driving LED1–LED8 from MCU pins PB0–PB7, with hierarchical labels so each channel's internal nets are unique.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Netlist: 8 channel instances with unique references; PBn→channel n mapping exact; internal nets unique per instance; ERC clean. The agent VM has no shell, text editor or Python and KiCad's IPC API is disabled, so .kicad_sch files can only change by saving from Eeschema.
Proposed partial credit
30% channel sheet; 40% 8 instances wired; 30% uniqueness and ERC.
R07.03.01.01-T16 Fusion Electronics: H-bridge motor driver from a block diagram
Original instruction
In Fusion Electronics, draw the full-bridge driver from input/hbridge_block.pdf: 4 N-MOSFETs, gate driver IC with bootstrap caps, current-sense shunt, flyback considerations per notes, connectors. ERC must show no errors.
- Platforms
win· Windowsmac· macOS- Applications
- Fusion Electronics
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Exported netlist vs reference topology (MOSFET bridge orientation, bootstrap path, shunt placement); ERC report 0 errors. ULP and SCR script execution and Fusion's Scripts and Add-Ins are disabled for the agent, so the schematic must be drawn interactively.
Proposed partial credit
40% bridge topology; 25% driver and bootstrap; 15% shunt; 20% ERC.
R07.03.01.01-T17 KiCad: buck converter from a datasheet typical-application circuit
Original instruction
Draw the TPS62130 typical application (3.3 V output, 3 A) from input/tps62130_datasheet.pdf in KiCad with exact component values and the feedback divider computed for 3.3 V from E96 values, including PG pull-up and soft-start cap.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Netlist vs reference; divider ratio gives 3.3 V ±1% using E96 values; inductor/cap values exact; ERC clean. The agent VM has no shell, text editor or Python and KiCad's IPC API is disabled, so .kicad_sch files can only change by saving from Eeschema.
Proposed partial credit
40% topology; 30% divider; 20% other values; 10% ERC.
R07.03.01.01-T18 Altium: net classes and differential-pair directives in the schematic
Original instruction
In input/usb_board.PrjPcb, add schematic directives so nets USB_DP/USB_DM form a differential pair 'USB', VBUS and +5V belong to net class 'PWR', and ETH TX±/RX± form pairs in class 'ETH_DIFF'; transfer to PCB via ECO.
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & forms- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
PcbDoc after ECO contains the diff pair objects and net classes with exact membership; schematic contains directives (not PCB-only definitions). Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the project must be edited in the Altium GUI.
Proposed partial credit
40% diff pairs; 40% net classes; 20% transferred via ECO.
R07.03.01.01-T19 KiCad: complete ESP32-S3 sensor board schematic from requirements
Original instruction
From input/requirements.md, design the full schematic in KiCad: ESP32-S3-WROOM-1, USB-C (native USB), 3.3 V LDO, auto-reset/boot buttons, two I²C sensors (BME280, VEML7700) with pull-ups, battery input with reverse protection, and test points. Pass ERC and the checklist in input/sch_checklist.md.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Scripted checklist on the netlist (22 rules: strapping pins, EN RC, USB D± to GPIO19/20, I²C pull-ups, decoupling counts, protection) plus ERC 0 errors. Score = rules passed / 22. The agent VM has no shell, text editor or Python and KiCad's IPC API is disabled, so .kicad_sch files can only change by saving from Eeschema.
Proposed partial credit
Score = checklist rules passed / 22 (85%); 15% ERC clean.
R07.03.01.01-T20 Control pair of T01: ATmega328P netlist with SKiDL
Original instruction
Control pair of T01. Without the schematic editor, write scripts/mcu_min.py using SKiDL to generate the same ATmega328P minimal system netlist and run its ERC.
- Platforms
lin· Linuxmac· macOSwin· Windows- Applications
- SKiDL · Python
- Interfaces
term· Terminalapi· API/SDK- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Same netlist isomorphism check as T01; SKiDL ERC clean; reported as the code baseline for schematic capture.
Proposed partial credit
30% parts and values; 50% isomorphism; 20% ERC.
Mapped research references
Existing benchmark-to-class links from the research catalog. They are not record-level annotations, executions or product endorsements.