Routing to a clean DRC (incl. high-speed)
Route nets, differential pairs and length-matched buses to a DRC-clean, functional board.
20 project-authored proposals · taxonomy v1.1 · 0 new benchmark runs. Verifiers and partial-credit rules below are designs, not executed results.
- Typical applications
- KiCad · Altium · Allegro
- Class GUI-need label
G3· GUI-only
Task proposals · 20
Expand to inspect the complete original wording and proposed checks. Original proposal text remains English in both interfaces.
R07.03.02.02-T01 Finish routing the last 12 signal nets on a 2-layer sensor board
Original instruction
Open fixtures/env_sensor/env_sensor.kicad_pro in KiCad 9. Placement is frozen and 12 signal nets remain as ratsnest. Route them on F.Cu/B.Cu with the Default netclass (0.25 mm track, 0.2 mm clearance, 0.6/0.3 mm vias). Do not move, rotate or flip any footprint. Save the board.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickpath· Continuous pathgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
kicad-cli pcb drc --severity-all on saved board: 0 errors, 0 unconnected items. Footprint positions/orientations diffed against fixture (tolerance 0). pcbnew Python console, IPC API and Freerouting are disabled in the image; grader rejects SES-import markers and checks no tracks exist outside the 12 nets' changes.
Proposed partial credit
40% all 12 nets connected; 40% DRC 0 errors; 20% footprints untouched and via count ≤ 10
R07.03.02.02-T02 Route USB 2.0 D+/D- as a 90 ohm differential pair with skew under 0.1 mm
Original instruction
In KiCad 9 open fixtures/usb_hub/usb_hub.kicad_pcb (4-layer, JLC 7628 stackup). Create netclass USB_DP (0.18 mm width, 0.15 mm gap) and assign USB_D+/USB_D- from J1 to U2. Route them as a coupled pair on F.Cu over the In1.Cu GND plane using the differential-pair router, at most 2 vias total, and tune intra-pair skew below 0.1 mm. Save.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parse .kicad_pcb: both nets in netclass USB_DP with 0.18/0.15; segment widths 0.18 mm; coupled-segment gap 0.15±0.01 mm over ≥85% of length; |len(D+)-len(D-)| < 0.1 mm; ≤2 vias; DRC 0 errors. Board edited only through GUI (Python/IPC disabled; tuning-pattern generator objects expected).
Proposed partial credit
20% netclass defined & assigned; 30% pair routed coupled on F.Cu; 30% skew < 0.1 mm; 20% DRC clean & ≤2 vias
R07.03.02.02-T03 Length-match an 8-bit data bus to its strobe within ±0.5 mm using tuning patterns
Original instruction
fixtures/lpddr_demo/lpddr_demo.kicad_pcb has DQ0..DQ7 and DQS routed but unmatched. In KiCad 9 add serpentine tuning patterns so every DQ net is within ±0.5 mm of DQS (pad-to-pad, including via lengths from the stackup). Keep 3× trace-width spacing inside meanders and do not reroute DQS. Save.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
path· Continuous pathgeom· Precise geometrynav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader computes routed length per net incl. via barrel per stackup; all 8 DQ within ±0.5 mm of DQS; DQS geometry identical to fixture; meander self-spacing ≥ 3×width; DRC 0 errors. Requires KiCad tuning-pattern generator objects on each DQ (hand-drawn wiggles via scripts absent; Python/IPC disabled).
Proposed partial credit
15% DQS untouched; 50% fraction of DQ nets within ±0.5 mm (scaled); 15% meander spacing rule; 20% DRC clean
R07.03.02.02-T04 Route power rails wide, pour GND on both layers and add stitching vias
Original instruction
Open fixtures/motor_ctrl/motor_ctrl.kicad_pcb in KiCad 9. Route VBAT, +12V and +5V with ≥0.8 mm tracks (create netclass PWR). Add GND zones on F.Cu and B.Cu covering the board outline with 0.3 mm clearance, place GND stitching vias at ≤10 mm pitch across the overlap, refill all zones and save.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
path· Continuous pathclick· Point & clickgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parse board: PWR netclass with ≥0.8 mm on all 3 nets' segments; 2 GND zones with filled polygons present (zones refilled, fill hash matches kicad-cli refill); max distance from any point of zone overlap to nearest GND via ≤10 mm (grid sampling); DRC 0 errors/0 unconnected; no isolated copper islands. KiCad Python console and IPC API disabled; board writes by any process other than pcbnew are flagged by a file audit log.
Proposed partial credit
25% power nets ≥0.8 mm; 25% two GND zones filled; 30% stitching pitch ≤10 mm; 20% DRC clean
R07.03.02.02-T05 Clear three clearance violations by rerouting only the flagged nets
Original instruction
fixtures/led_driver/led_driver.kicad_pcb fails DRC with 3 clearance violations on nets SDA, SCL and LED_PWM. In KiCad 9 reroute only those segments so DRC passes. No footprint may move and no other net's copper may change. Save.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickpath· Continuous path- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
kicad-cli DRC: 0 errors, 0 unconnected. Copper of all nets except SDA/SCL/LED_PWM byte-identical (segment/via UUID+geometry) to fixture; footprints unchanged. Scripting consoles disabled.
Proposed partial credit
50% violations cleared; 30% no other net touched; 20% footprints unchanged
R07.03.02.02-T06 Control pair of T01: autoroute the sensor board via Freerouting and CLI DRC
Original instruction
Control pair of T01. Same env_sensor board, terminal only: export Specctra DSN with kicad-cli/pcbnew Python, autoroute with Freerouting CLI, import the SES back, run kicad-cli DRC and save. Same constraints as T01 (no footprint moves, Default netclass).
- Platforms
lin· Linuxmac· macOS- Applications
- KiCad · kicad-cli · Freerouting
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Identical checks to T01 (DRC 0 errors/0 unconnected, footprints unchanged, via count reported). GUI binaries absent from this container; result compared with T01 to measure GUI vs CLI gap.
Proposed partial credit
40% all nets connected; 40% DRC 0 errors; 20% footprints untouched
R07.03.02.02-T07 Route a 4-layer STM32 board in Altium to zero DRC violations with ≤40 vias
Original instruction
Open fixtures/stm32_io/stm32_io.PrjPcb in Altium Designer 24. Placement is locked; 68 nets are unrouted. Route all nets under the existing rule set (0.15 mm clearance, 0.15-0.5 mm widths, 0.3/0.6 mm vias, L2 GND and L3 PWR planes, signals on L1/L4). Use at most 40 signal vias. Run Design Rule Check and save.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometrynav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 4 / 5
Proposed verifier
Harness runs a fixed OutJob after save to export DRC report and ASCII PcbDoc: 0 rule violations, 0 unrouted connections, signal via count ≤40, component locations equal fixture. Altium scripting system and Situs/ActiveRoute autorouter licences disabled; ActiveRoute/autoroute log entries cause failure.
Proposed partial credit
35% routed fraction of 68 nets; 35% DRC 0 violations; 15% vias ≤40; 15% placement unchanged
R07.03.02.02-T08 Route two 100 ohm LVDS pairs in Altium and length-match them with xSignals
Original instruction
In Altium Designer open fixtures/adc_lvds/adc_lvds.PcbDoc. Define differential pairs LVDS_CLK and LVDS_D0 from the schematic net names, add a 100 Ω DiffPair rule using the impedance profile (stackup provided), route both pairs interactive from U1 to J2, create xSignals for each and tune so pair-to-pair length differs ≤0.25 mm and intra-pair skew ≤0.05 mm. Save.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
OutJob export: diff-pair objects and 100 Ω impedance-profile rule exist; xSignal lengths: |L_CLK-L_D0| ≤0.25 mm, each intra-pair skew ≤0.05 mm; widths/gaps equal profile ±0.005 mm; DRC 0 violations. Scripting disabled; edits must appear in PcbDoc history as interactive diff-pair objects.
Proposed partial credit
20% pairs + rule defined; 30% both pairs routed; 30% length/skew targets met; 20% DRC clean
R07.03.02.02-T09 Fan out and escape-route a 0.8 mm-pitch 196-ball BGA on six layers
Original instruction
fixtures/fpga_carrier/fpga_carrier.PcbDoc (Altium) holds a 14×14, 0.8 mm-pitch BGA (U1) with 120 signal nets to edge connectors. Create dog-bone fanout with 0.2/0.4 mm vias, then escape-route every signal ball to outside the BGA courtyard on L1, L3, L4 and L6 (L2/L5 are planes). Do not route beyond 3 mm past the courtyard. Run DRC and save.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometrynav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Grader parses ASCII export: each of 120 signal balls has a connected track reaching the courtyard+0.5 mm ring; no track ends beyond courtyard+3 mm; via sizes 0.2/0.4; no via-in-pad; DRC (clearance, width, short) 0 violations inside region. Autorouter/fanout scripts disabled; escape-route command allowed but logged.
Proposed partial credit
25% fanout vias for all balls; 45% fraction of balls escaped (scaled); 30% DRC clean in BGA region
R07.03.02.02-T10 Route DDR3 fly-by address bus in Allegro and match to clock in Constraint Manager
Original instruction
Open fixtures/ddr3_x16/ddr3_x16.brd in Cadence Allegro PCB Designer 23.1. In Constraint Manager create a match group ADDR_CMD with all A0-A14, BA0-2 and control nets relative to CK_P within ±25 mil, then route the fly-by topology U1→U2→U3→termination on inner layers. All nets must meet the existing spacing CSets. Save the board.
- Platforms
win· Windowslin· Linux- Applications
- Allegro
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Harness runs Allegro batch DRC update and extracts report: match group ADDR_CMD exists with ±25 mil tolerance; all members PASS (green) in CM length worksheet; topology order U1→U2→U3→RT per net; DRC 0 errors. SKILL and autorouter disabled by license file; batch-route log entries cause failure.
Proposed partial credit
20% match group defined; 35% fly-by order correct per net; 30% members within ±25 mil; 15% DRC clean
R07.03.02.02-T11 Set up Allegro physical and spacing CSets then route Ethernet MDI pairs
Original instruction
In Allegro open fixtures/gige_phy/gige_phy.brd. Create physical CSet DIFF100 (5 mil width, 6 mil gap on Top) and spacing CSet ETH (20 mil to other nets). Assign them to MDI0-MDI3 P/N pairs, then route the four pairs from the PHY to the magnetics on Top with ≤2 vias per pair and intra-pair skew ≤5 mil. Save.
- Platforms
win· Windowslin· Linux- Applications
- Allegro
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickpath· Continuous pathgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Batch report export: CSets DIFF100/ETH exist with stated values and are assigned to the 8 nets; routed widths/gaps match; skew ≤5 mil per pair; ≤2 vias per pair; 0 DRC errors. SKILL disabled.
Proposed partial credit
25% CSets created & assigned; 40% four pairs routed; 20% skew ≤5 mil; 15% DRC clean
R07.03.02.02-T12 Route a 50 ohm grounded coplanar waveguide with a via fence from SMA to LNA
Original instruction
fixtures/gnss_front/gnss_front.kicad_pcb (KiCad 9, 4-layer). Using the provided stackup, route net RF_IN from J1 (SMA) to U3 pin 1 as grounded CPW: 0.32 mm trace, 0.2 mm gap to F.Cu GND pour, no vias on the RF net, no bends sharper than 45°. Add GND vias along both sides at ≤1.5 mm pitch within 0.5 mm of the gap edge. Refill zones and save.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
path· Continuous pathgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader: RF_IN segments 0.32 mm, no vias, all bend angles ≥135°; F.Cu GND fill keeps 0.2±0.02 mm gap along trace; via fence on both sides with max spacing ≤1.5 mm and offset ≤0.5 mm; computed Z0 (Wadell CPWG on stackup) 50±3 Ω; DRC 0 errors. Python/IPC disabled.
Proposed partial credit
25% trace width/gap geometry; 15% no vias & 45° bends; 40% via-fence pitch/offset; 20% DRC clean
R07.03.02.02-T13 Route a 2-layer board keeping an unbroken ground return under the SPI clock
Original instruction
Open fixtures/spi_logger/spi_logger.kicad_pcb (2-layer). Route all 18 unrouted nets. B.Cu is a GND pour: no B.Cu track or via-to-via jumper may cross under the SPI_SCK or SPI_MOSI paths (within 1 mm laterally), and those two nets must stay entirely on F.Cu. Refill zones, run DRC, save.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
path· Continuous pathgeom· Precise geometryvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
DRC 0 errors/0 unconnected; SPI_SCK/SPI_MOSI segments only on F.Cu; geometric check that no B.Cu copper other than GND fill lies within 1 mm of their projection and that GND fill under them is one connected polygon. Scripting disabled.
Proposed partial credit
30% all nets routed; 20% SPI nets top-only; 30% unbroken return plane; 20% DRC clean
R07.03.02.02-T14 Lay out a buck converter hot loop and switch node to tight copper limits
Original instruction
fixtures/buck_5v/buck_5v.kicad_pcb has U1 (buck), CIN1, L1, COUT1 placed. Route VIN, SW, VOUT and PGND with copper zones or wide tracks so that: SW node copper area ≤30 mm²; CIN1-to-U1 VIN/PGND path ≤3 mm each; feedback net FB routed away from SW (≥2 mm) on the opposite side of L1. Run DRC and save.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometryvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader unions all SW copper (tracks+zones fills) → area ≤30 mm²; shortest copper path CIN1 pads→U1 VIN/PGND pads ≤3 mm (graph on copper); min distance FB↔SW ≥2 mm; DRC 0 errors/0 unconnected; extracted loop area reported. Python/IPC disabled.
Proposed partial credit
25% SW area ≤30 mm²; 30% hot-loop path lengths; 20% FB separation; 25% DRC clean
R07.03.02.02-T15 Repour polygons and clear antennae after a connector footprint swap in Altium
Original instruction
In Altium open fixtures/sensor_hub/sensor_hub.PcbDoc. J4 was swapped to a new footprint, leaving dangling tracks, 9 unrouted connections and stale polygons. Remove net antennae, reconnect the 9 connections, repour all polygons and run DRC until 0 violations. Do not move any component other than J4's tracks.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickpath· Continuous path- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
OutJob DRC report after save: 0 violations including Net Antennae, Un-Routed Net, Modified Polygon; component locations identical; polygon pour state 'repoured' (no shelved/modified flags). Scripting disabled.
Proposed partial credit
30% antennae removed; 40% 9 connections routed; 15% polygons repoured; 15% DRC clean
R07.03.02.02-T16 Route four HDMI TMDS pairs with intra- and inter-pair skew limits
Original instruction
fixtures/hdmi_tx/hdmi_tx.kicad_pcb (4-layer). Route TMDS_D0/D1/D2/CLK ± pairs from U5 to J3 as 100 Ω coupled pairs (0.13 mm/0.15 mm on F.Cu) with ≤2 vias per pair (each with an adjacent GND return via). Intra-pair skew ≤0.15 mm, inter-pair length spread ≤2 mm. Save after DRC passes.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometrynav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Grader: four pairs fully routed with stated width/gap over ≥80% length; intra-pair skew ≤0.15 mm; max-min pair length ≤2 mm; ≤2 signal vias per pair each with GND via within 1 mm; DRC 0 errors. Tuning-pattern generators required where tuned; scripting disabled.
Proposed partial credit
30% pairs routed coupled; 25% intra-pair skew; 20% inter-pair spread; 25% return vias & DRC clean
R07.03.02.02-T17 Route an Ethernet jack with a copper keep-out under magnetics and 2 mm isolation
Original instruction
Open fixtures/eth_node/eth_node.kicad_pcb. Draw a rule area under T1 (magnetics) that forbids tracks, vias and pours on all copper layers, then route the 4 MDI pairs and chassis GND so that chassis copper stays ≥2 mm from any signal-GND copper. Refill zones, run DRC and save.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Board contains a rule area covering T1 courtyard (±0.2 mm) with keepout tracks/vias/pours on all layers; no copper inside it; min distance CHASSIS↔GND copper ≥2 mm; 8 MDI nets routed; DRC 0 errors/0 unconnected. KiCad Python console and IPC API disabled in the VM; writes to the .kicad_pcb by any process other than pcbnew are flagged by a file audit log.
Proposed partial credit
25% rule area correct; 35% MDI nets routed; 25% 2 mm isolation; 15% DRC clean
R07.03.02.02-T18 Route out of a 0.5 mm-pitch QFN without via-in-pad using neck-downs
Original instruction
fixtures/ble_tag/ble_tag.kicad_pcb (4-layer) has U1, a 0.5 mm-pitch QFN-48 with 30 unrouted nets. Add a rule-area/custom DRC rule allowing 0.1 mm track width only inside U1's courtyard (0.15 mm elsewhere). Route all 30 nets without vias in pads or under the exposed pad except GND thermal vias. Save after DRC passes.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
path· Continuous pathgeom· Precise geometrytype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Custom rule in .kicad_dru restricts 0.1 mm to courtyard; parse board: segments <0.15 mm only inside U1 courtyard; no vias overlapping pads except GND in EP; all 30 nets connected; DRC 0 errors. Scripting disabled.
Proposed partial credit
20% neck-down rule; 50% fraction of 30 nets routed; 15% no via-in-pad; 15% DRC clean
R07.03.02.02-T19 Create a room-scoped high-voltage clearance rule in Altium and route mains nets
Original instruction
fixtures/smart_plug/smart_plug.PcbDoc (Altium). Create a room HV_ZONE around the relay/AC section and a clearance rule (2.5 mm, scope InRoom('HV_ZONE')) with higher priority than the default. Route AC_L, AC_N and RELAY_OUT at 2 mm width, add a 1 mm milled slot between primary and secondary as a board cutout, and get DRC to 0. Save.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickpath· Continuous pathgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Export rules + ASCII: room HV_ZONE exists; rule 2.5 mm scoped to room, priority above default; three AC nets routed ≥2 mm wide; cutout ≥1 mm wide separates primary/secondary copper; DRC 0. Scripting disabled.
Proposed partial credit
25% room + scoped rule; 35% AC nets routed; 20% slot cutout; 20% DRC clean
R07.03.02.02-T20 Apply an ECO move to J3 and reroute its 10 nets with the shove router
Original instruction
ECO note fixtures/io_board/eco_07.pdf moves J3 5 mm toward the board edge. In KiCad 9 open io_board.kicad_pcb, move J3 exactly as specified, then repair its 10 attached nets with interactive push-and-shove routing. Nets not attached to J3 may be shoved but must keep the same layer sequence and via count. Save after DRC passes.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
drag· Drag & droppath· Continuous pathgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
J3 position equals fixture +5.00 mm along the ECO vector (±0.01 mm); 10 J3 nets connected; for every other net the ordered layer list and via count equal the fixture; DRC 0 errors/0 unconnected. Scripting disabled.
Proposed partial credit
20% J3 moved exactly; 40% J3 nets reconnected; 25% other nets' topology preserved; 15% DRC clean
Mapped research references
Existing benchmark-to-class links from the research catalog. They are not record-level annotations, executions or product endorsements.