Placement & board constraints
Place components and define outline, keep-outs and rules to a mechanical spec.
20 project-authored proposals · taxonomy v1.1 · 0 new benchmark runs. Verifiers and partial-credit rules below are designs, not executed results.
- Typical applications
- KiCad PCB Editor · Altium · Allegro
- Class GUI-need label
G3· GUI-only
Task proposals · 20
Expand to inspect the complete original wording and proposed checks. Original proposal text remains English in both interfaces.
R07.03.02.01-T01 KiCad: board outline and M3 holes for an SN25 enclosure
Original instruction
In KiCad 8 PCB Editor, open input/encabulator.kicad_pro, update PCB from schematic, draw an Edge.Cuts outline per input/sn25_enclosure.pdf (rounded rectangle with R2 corners), and place four M3 mounting holes (MountingHole_3.2mm_M3) on a 40.0 × 32.0 mm rectangle centred on the board.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickgeom· Precise geometrydrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader parses .kicad_pcb: closed Edge.Cuts loop matching enclosure outline (Hausdorff < 0.05 mm); 4 hole footprints at specified centres ±0.02 mm; all schematic footprints present. pcbnew scripting console and action plugins are disabled; file writes by non-KiCad processes are flagged.
Proposed partial credit
40% outline; 40% hole positions; 20% footprints imported.
R07.03.02.01-T02 KiCad: edge connectors with 1 mm overhang and decouplers near the MCU
Original instruction
In input/node.kicad_pcb, place J1 (USB-C) and J2 (JST-PH) on the top board edge with exactly 1.0 mm overhang beyond Edge.Cuts, and place C1–C4 so each pad is within 5 mm of its assigned U1 power pin (per input/decap_map.csv), all on F.Cu with no courtyard overlaps.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parsed board: connector body front edges 1.0 ±0.05 mm beyond Edge.Cuts; pad-to-pin distances ≤ 5 mm per map; kicad-cli pcb drc courtyard errors = 0. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
Proposed partial credit
40% connector overhang; 40% decoupler distances; 20% no courtyard overlaps.
R07.03.02.01-T03 KiCad: import enclosure DXF as outline with a 2 mm edge keep-out
Original instruction
Import input/enclosure.dxf onto Edge.Cuts (mm units, origin at the DXF origin), make sure the outline is closed, add a rule area keeping out tracks, vias, pads and footprints within 2 mm of the edge, and move any footprint that violates it inward.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Edge.Cuts equals DXF geometry (Hausdorff < 0.01 mm); rule area polygon offset 2 mm inward with keep-out flags; DRC 0 rule-area violations; footprints otherwise unmoved where compliant. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
Proposed partial credit
40% outline import; 30% keep-out area; 30% violations cleared.
R07.03.02.01-T04 Altium: four identical channels placed with Room Copy Formats
Original instruction
In input/adc4.PcbDoc, place channel 1 (room CH1) per input/ch1_placement.png, then replicate the placement to rooms CH2–CH4 with Copy Room Formats so all four channels have identical relative placement, arranged left to right at 18 mm pitch.
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
drag· Drag & dropgeom· Precise geometryvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Grader exports pick-and-place: per-channel relative positions/rotations identical (±0.01 mm, 0°); room origins at 18.0 mm pitch; CH1 matches the reference image layout (component position error ≤ 0.5 mm). Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the board must be edited in the Altium GUI.
Proposed partial credit
30% CH1 placement; 50% replication exact; 20% pitch.
R07.03.02.01-T05 Allegro: Constraint Manager rules and a BGA region
Original instruction
In Allegro PCB Editor, open input/fpga_board.brd and in Constraint Manager create physical/spacing classes per input/rules.xlsx (DDR, PWR, default) and a constraint region under the BGA (U1 courtyard) allowing 0.09 mm trace/space. Save.
- Platforms
win· Windowslin· Linux- Applications
- Cadence Allegro
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Grader exports constraints via Allegro batch (techfile export): classes and values match spreadsheet; region shape covers the BGA courtyard (IoU ≥ 0.95) with the specified region rules. SKILL loading, script replay and techfile import are disabled in the agent's Allegro environment and its VM has no shell, so rules must be set in Constraint Manager.
Proposed partial credit
50% class values; 30% region geometry; 20% net assignments to classes.
R07.03.02.01-T06 KiCad: ESP32 module antenna overhang and copper keep-out
Original instruction
Place the ESP32-S3-WROOM-1 module in input/iot.kicad_pcb so its antenna overhangs the board edge per the Espressif guideline (antenna area outside the outline, or ≥ 15 mm keep-out), add a copper keep-out rule area under the antenna on all layers, and place power MOSFETs Q1–Q2 at least 20 mm from it.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Parsed board: antenna region polygon (from footprint) outside Edge.Cuts or fully in a no-copper rule area on all copper layers; Q1/Q2 courtyard distance ≥ 20 mm from antenna; DRC clean. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
Proposed partial credit
50% antenna placement rule; 30% keep-out area; 20% MOSFET distance.
R07.03.02.01-T07 Altium: board shape from an enclosure STEP with 3D height clearance
Original instruction
Import input/case_lid.step as a 3D body in input/handheld.PcbDoc, define the board shape from the enclosure's PCB-seat face, and place components so none collides with the lid (3D clearance ≥ 0.5 mm, component height rule ≤ 8 mm under the dome region).
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
drag· Drag & dropgeom· Precise geometryvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Grader exports board + components to STEP and runs collision against the lid: min clearance ≥ 0.5 mm; board outline matches seat face (Hausdorff < 0.05); height rule exists and DRC clean. Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the board must be edited in the Altium GUI.
Proposed partial credit
30% board shape; 50% no collisions; 20% height rule.
R07.03.02.01-T08 KiCad: decouplers within 2 mm of their pins on one side
Original instruction
In input/fpga_break.kicad_pcb, place the 16 decoupling capacitors so each is within 2 mm of its assigned power pin (input/decap_map.csv), on B.Cu under the FPGA, rotated to minimise loop area (pads aligned to the pin-to-via direction), with zero courtyard overlaps.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parsed board: all 16 caps on B.Cu; pad-to-pin distance ≤ 2 mm; courtyard DRC 0; orientation check ±15° vs reference direction. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
Proposed partial credit
50% distances; 20% layer; 20% no overlaps; 10% orientation.
R07.03.02.01-T09 Allegro: place and lock mechanical symbols at fixed coordinates
Original instruction
In input/ctrl.brd, place mechanical symbols for 4 mounting holes, 2 fiducials and the board-to-board connector at the coordinates in input/mech.csv (relative to the board origin), set them to Fixed, and place the 3 tall capacitors within the height-restricted region rules.
- Platforms
win· Windowslin· Linux- Applications
- Cadence Allegro
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Grader extracts placement report: symbol positions ±0.01 mm, fixed property set; tall caps in allowed area; DRC (package height) clean. SKILL loading, script replay and techfile import are disabled in the agent's Allegro environment and its VM has no shell, so symbols must be placed interactively.
Proposed partial credit
50% mechanical placement; 20% fixed; 30% tall caps compliant.
R07.03.02.01-T10 KiCad: 4-layer stackup and net-class rules in Board Setup
Original instruction
In input/motor.kicad_pcb Board Setup, define a 4-layer stackup per input/stackup.pdf (thicknesses, dielectric εr), net classes Power (0.5 mm track, 0.3 mm clearance), Default (0.2/0.2) and a differential pair class USB (0.2 mm width, 0.15 mm gap), and assign nets by pattern.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parsed .kicad_pcb/.kicad_pro: stackup layer thicknesses/εr exact; net classes and assignments (pattern-matched nets) exact. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
Proposed partial credit
40% stackup; 40% net classes; 20% assignments.
R07.03.02.01-T11 Fusion Electronics: round board in a Ø60 mm enclosure with angled connectors
Original instruction
In Fusion Electronics, make the PCB for input/sensor_puck.fsch a Ø58 mm circle concentric with the Ø60 enclosure, with three M2.5 holes at 120° on a Ø50 PCD, connector J1 at 0° and J2 at 90° pointing radially outward at the edge.
- Platforms
win· Windowsmac· macOS- Applications
- Fusion Electronics
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
geom· Precise geometrydrag· Drag & dropclick· Point & click- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Board export (.brd XML): circular outline Ø58 ±0.05; hole centres at radius 25 ±0.02 and 120° spacing; connector rotations 0°/90° ±0.5° with mating face at radius ≥ 28.5 mm. ULP and SCR script execution and Fusion's Scripts and Add-Ins are disabled for the agent, so the board must be laid out interactively.
Proposed partial credit
30% outline; 30% holes; 40% connector placement.
R07.03.02.01-T12 Altium: 2×3 embedded board array panel with rails and fiducials
Original instruction
Create output/panel.PcbDoc in Altium with an Embedded Board Array of input/node.PcbDoc (2 × 3, 2 mm V-score spacing), 5 mm top/bottom rails, three panel fiducials and four tooling holes per input/panel_spec.pdf.
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Grader reads panel document: array object with row/column counts and spacing exact; rail size; fiducial/tooling-hole positions ±0.05 mm. Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the board must be edited in the Altium GUI.
Proposed partial credit
40% array config; 20% rails; 40% fiducials and tooling holes.
R07.03.02.01-T13 KiCad: no-copper keep-outs around mounting holes
Original instruction
In input/power.kicad_pcb, add rule areas forbidding tracks, vias and zones within 3 mm of each of the four mounting holes on all copper layers, refill zones, and fix any track that now violates the rule by moving it (not deleting nets).
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Rule areas: 4 circles r = 3 mm (+hole radius) at hole centres on all copper layers; DRC 0 violations and 0 unconnected; netlist connectivity unchanged. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
Proposed partial credit
40% rule areas; 40% violations fixed; 20% connectivity intact.
R07.03.02.01-T14 EasyEDA Pro: place 20 front-panel parts to a placement drawing
Original instruction
In EasyEDA Pro (web), place the 20 LEDs, buttons and connectors of project 'FrontPanel' at the X/Y/rotation positions given in input/placement.pdf (dimensioned drawing, not a CSV), on the top layer.
- Platforms
web· Any OS (web)- Applications
- EasyEDA Pro
- Interfaces
brow· Browser- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
drag· Drag & dropgeom· Precise geometryvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader exports pick-and-place CSV through the account: each part within ±0.05 mm and 0.5° of the drawing; score per part. Placement must be done in the editor (project history shows interactive moves; no CSV import). EasyEDA Pro extensions and API are disabled for the agent's account.
Proposed partial credit
Score = fraction of 20 parts within tolerance (90%); 10% layer correct.
R07.03.02.01-T15 KiCad: reduce ratsnest length by 30% while respecting constraints
Original instruction
input/sensor.kicad_pcb has all 60 components dumped off-board. Place them inside the outline so total ratsnest length drops ≥ 30% vs the provided baseline placement value, while keeping connector positions fixed, decouplers ≤ 3 mm from pins and no courtyard overlaps.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropgeom· Precise geometryvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 4 / 5
Proposed verifier
Grader computes minimum-spanning ratsnest length per net from the saved board; reduction ≥ 30% vs baseline (scaled credit); fixed connectors unmoved; decoupler distance and courtyard DRC checks. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
Proposed partial credit
50% ratsnest reduction (scaled); 20% decouplers; 20% no overlaps; 10% connectors fixed.
R07.03.02.01-T16 Altium: component clearance rule and BGA fanout keep-out
Original instruction
In input/mcu.PcbDoc, add a Component Clearance rule (0.25 mm horizontal, 0.5 mm vertical), a placement room keeping other components ≥ 2 mm from the BGA for fanout escape, and move offending parts to satisfy both.
- Platforms
win· Windows- Applications
- Altium Designer
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clicktype· Text & formsdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Rules exported with exact values; grader's DRC report shows 0 component clearance and room violations; components moved minimally (mean displacement ≤ reference × 1.5). Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the board must be edited in the Altium GUI.
Proposed partial credit
30% rules; 50% violations cleared; 20% minimal movement.
R07.03.02.01-T17 KiCad: align LEDs and buttons to front-panel cutouts
Original instruction
Import input/front_panel.dxf on a User layer as a reference, then place D1–D8 and SW1–SW4 so their optical/actuator centres sit exactly at the DXF cutout centres (±0.1 mm), on F.Cu, and lock them.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parsed board: each part's reference point (footprint origin offset per datasheet table) within 0.1 mm of the matching cutout centre; locked flag set; User layer contains the DXF. KiCad's scripting console and pcbnew Python module are removed, and a file-system audit log flags .kicad_pcb writes not made by the PCB Editor (hand-edited S-expressions fail).
Proposed partial credit
70% 12 parts aligned (≈5.8 each); 20% locked; 10% reference layer.
R07.03.02.01-T18 Allegro: replicate an 8-channel placement with module reuse
Original instruction
In input/frontend.brd, place channel 1 per input/ch_layout.pdf, create a place-replicate module from it, and apply it to channels 2–8 in a 2 × 4 grid at 22 × 30 mm pitch, keeping net assignments correct per channel.
- Platforms
win· Windowslin· Linux- Applications
- Cadence Allegro
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Placement report: identical relative positions across 8 channels; grid pitch exact; each replicated component bound to the correct channel's nets (refdes mapping check). SKILL loading, script replay and techfile import are disabled in the agent's Allegro environment and its VM has no shell, so channels must be replicated interactively.
Proposed partial credit
25% channel 1; 50% replication; 25% grid and mapping.
R07.03.02.01-T19 KiCad: full 60-part placement under mechanical, thermal and EMI groups
Original instruction
Place all components of input/drive.kicad_pcb according to input/placement_rules.md: mechanical (connectors and holes fixed), thermal (power stage near the heatsink edge, sensors ≥ 15 mm away), EMI (switching node loop < 40 mm², analog section separated by ≥ 5 mm from digital), plus courtyard DRC clean.
- Platforms
win· Windowsmac· macOSlin· Linux- Applications
- KiCad PCB Editor
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropgeom· Precise geometryvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Weighted scripted checks on the saved board (14 rules from placement_rules.md, loop area computed from placed part pad polygons); courtyard DRC 0. Score = weighted rules passed. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
Proposed partial credit
Weighted rules: mechanical 25%, thermal 25%, EMI 30%, DRC 20%.
R07.03.02.01-T20 Control pair of T01: outline and holes via pcbnew Python
Original instruction
Control pair of T01. Using KiCad's pcbnew Python API from a terminal (no GUI), add the same enclosure outline and four M3 holes to input/encabulator.kicad_pcb and save output/encabulator_py.kicad_pcb.
- Platforms
lin· Linuxmac· macOSwin· Windows- Applications
- KiCad pcbnew API
- Interfaces
term· Terminalapi· API/SDK- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
AP· API-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Same outline and hole checks as T01; reported as the scripting baseline.
Proposed partial credit
50% outline; 50% hole positions.
Mapped research references
Existing benchmark-to-class links from the research catalog. They are not record-level annotations, executions or product endorsements.