ECO, libraries & fabrication outputs
Integrate parts, sync schematic and board after changes, and produce Gerbers, drill and BOM.
20 project-authored proposals · taxonomy v1.1 · 0 new benchmark runs. Verifiers and partial-credit rules below are designs, not executed results.
- Typical applications
- KiCad · Altium · kicad-cli
- Class GUI-need label
HY· Hybrid
Task proposals · 20
Expand to inspect the complete original wording and proposed checks. Original proposal text remains English in both interfaces.
R07.03.02.03-T01 Fix the I/O expander footprint, sync the board and export a fab package
Original instruction
fixtures/io_exp/io_exp.kicad_pro: U4 (PCA9554, TSSOP-16) is linked to a SOIC-16 footprint. Assign the project-local footprint io_exp:TSSOP-16_4.4x5mm_P0.65mm, run Update PCB from Schematic, re-place U4 at the same center and reroute its nets. Then write out/: ERC and DRC JSON reports, Gerber X2 for all used layers, Excellon drill, and IPC-D-356 netlist.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad · kicad-cli
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickpath· Continuous pathcode· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Schematic and PCB both reference the TSSOP footprint; U4 center within 0.1 mm of fixture; ERC/DRC JSON report 0 errors; Gerber set contains all copper/mask/silk/paste/Edge.Cuts files and XOR-renders against a reference within 0.5% pixels outside U4 region; drill hit count matches; IPC-356 nets equal schematic netlist.
Proposed partial credit
25% footprint assigned & synced; 25% U4 rerouted DRC clean; 30% Gerber/drill set complete; 20% IPC-356 + reports
R07.03.02.03-T02 Build a SOT-23-6 footprint from datasheet dimensions in the project library
Original instruction
From docs/TLV62569_datasheet.pdf (package drawing DDC, page 23) create footprint SOT-23-6_TI_DDC in project library fixtures/pwr/pwr.pretty with KiCad's Footprint Editor: SMD pads per the recommended land pattern, F.Fab outline, F.SilkS with pin-1 mark, F.CrtYd with 0.25 mm margin, reference/value fields. Assign it to U2 in pwr.kicad_sch.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
type· Text & formsgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parse .kicad_mod: 6 pads numbered 1-6, positions and sizes within 0.01 mm of the datasheet land pattern; courtyard encloses pads+body with 0.25±0.02 mm margin; silk does not overlap pads; pin-1 marker on silk near pad 1; U2 footprint field references it.
Proposed partial credit
50% pad numbering/positions/sizes; 20% courtyard margin; 15% silk/fab layers; 15% assigned to U2
R07.03.02.03-T03 Create a schematic symbol with correct pin electrical types and footprint link
Original instruction
Using docs/TPS62133_ds.pdf, create symbol TPS62133 (16 pins + exposed pad 17) in fixtures/libs/power.kicad_sym with KiCad Symbol Editor. Group pins: inputs left, outputs right, power top/bottom; set electrical types (power in, power out, input, open collector for PG). Link default footprint Package_DFN_QFN:VQFN-16-1EP_3x3mm and fill Datasheet/MPN fields. Place it as U1 in buck.kicad_sch and run ERC.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
type· Text & formsclick· Point & clickgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parse symbol: 17 pins with numbers/names per datasheet table; electrical types match a key file (≥16/17); pins on 2.54 mm grid; footprint and MPN fields set; ERC on buck.kicad_sch reports 0 pin-type errors.
Proposed partial credit
40% pin numbers/names; 25% electrical types; 15% grid & grouping; 20% footprint link + ERC
R07.03.02.03-T04 Export a JLCPCB-ready Gerber and drill zip with kicad-cli
Original instruction
For fixtures/thermo/thermo.kicad_pcb, using kicad-cli only, export Gerbers (F/B Cu, Mask, Silk, Paste, Edge.Cuts) with Protel extensions, separate PTH and NPTH Excellon files in mm with a PDF drill map, and zip them as out/thermo_fab_v1.2.zip. Write the exact commands to out/export.sh.
- Platforms
lin· Linuxmac· macOSwin· Windows- Applications
- kicad-cli
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP09· Files & folders- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Unzip: required 9 Gerber files with .GTL/.GBL/.GTS/.GBS/.GTO/.GBO/.GTP/.GBP/.GM1 names; PTH.drl and NPTH.drl present in mm; drill counts equal board; gerbv XOR vs reference < 0.1% pixels; export.sh reruns to identical hashes.
Proposed partial credit
40% complete Gerber layer set; 30% split PTH/NPTH drills; 20% zip naming; 10% reproducible script
R07.03.02.03-T05 Produce an assembly BOM and bottom-side-corrected pick-and-place file
Original instruction
fixtures/smartwatch/smartwatch.kicad_pro has 74 parts on both sides. Fill missing LCSC and MPN fields for the 9 parts flagged in docs/bom_gaps.xlsx, export a BOM CSV grouped by value+footprint with columns Designator, Qty, Value, Footprint, MPN, LCSC, and a CPL CSV in mm where bottom parts carry layer=Bottom with rotations corrected per docs/jlc_rotation_rules.md.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad · kicad-cli · Excel
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
type· Text & formsclick· Point & clickmulti· Cross-app- Work product
WP02· Records/table- Conditions
multiapp· Multi-app- Proposed difficulty
- 3 / 5
Proposed verifier
Schematic fields for the 9 parts match bom_gaps.xlsx; BOM rows group correctly (qty sum 74, no duplicate groups); CPL has 74 rows, X/Y within 0.01 mm of board, bottom rotations equal key after rule application.
Proposed partial credit
30% fields filled in schematic; 30% BOM grouping/columns; 40% CPL positions & rotations
R07.03.02.03-T06 Swap an LDO for a buck converter and carry the change through to a clean board
Original instruction
ECO docs/eco_12.pdf replaces U3 (AMS1117-3.3) with a TPS62162 buck: add U3 new symbol/footprint, L1 2.2 µH 0806, COUT 22 µF, feedback divider per datasheet for 3.3 V. In fixtures/logger/logger.kicad_pro edit the schematic, update the PCB, place the new parts within the old LDO area (keep-out shown on User.1), route, refill zones and regenerate fab outputs to out/.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad · kicad-cli
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickpath· Continuous pathgeom· Precise geometrycode· Code & commands- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Netlist diff vs key: new parts and nets exactly per ECO; feedback resistors give 3.3 V ±1% from datasheet Vref; all new footprints inside User.1 area; ERC/DRC 0 errors/0 unconnected; out/ Gerbers regenerated after PCB save (timestamps + XOR differs only inside ECO area).
Proposed partial credit
40% schematic ECO & divider value; 25% placement inside area; 20% routed & DRC clean; 15% fab outputs regenerated
R07.03.02.03-T07 Geographically re-annotate the board and back-annotate designators
Original instruction
In fixtures/audio_amp/audio_amp.kicad_pcb run Geographical Reannotation (top-left to bottom-right, front then back, start at 1 per prefix), then back-annotate the new designators to the schematic so schematic and PCB match. Save both and export out/refdes_map.csv (old,new).
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Designators on PCB follow the ordering rule (computed from footprint positions); schematic designators equal PCB per UUID; Update PCB from Schematic dry-run reports 0 changes; refdes_map.csv covers all parts and matches the UUID mapping. KiCad Python console and IPC API disabled; writes to .kicad_sch/.kicad_pcb by any process other than KiCad are flagged by a file audit log.
Proposed partial credit
40% PCB order rule; 40% schematic in sync; 20% mapping CSV
R07.03.02.03-T08 Add a Qwiic I2C connector via ECO in Altium and route it on the board edge
Original instruction
In Altium Designer open fixtures/env_node/env_node.PrjPcb. On sheet Sensors.SchDoc add J5 (SM04B-SRSS-TB from the company DbLib) wired to 3V3, GND, I2C_SDA, I2C_SCL with 4.7 kΩ pull-ups. Compile with 0 errors, run Update PCB Document via the ECO dialog, place J5 on the north edge (connector face flush with Edge), and route the new connections. Run DRC; save.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickdrag· Drag & droppath· Continuous path- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
OutJob after save: compile messages 0 errors; netlist has J5 + 2 pull-ups on correct nets; J5 body edge within 0.1 mm of north board edge, orientation facing out; new connections routed; DRC 0; parts from DbLib (library link fields present). Scripting disabled.
Proposed partial credit
30% schematic ECO & compile; 20% ECO pushed to PCB; 25% J5 placement; 25% routed & DRC clean
R07.03.02.03-T09 Configure an Altium OutJob for Gerber X2, ODB++, drill, BOM and assembly PDF
Original instruction
For fixtures/motor_drv/motor_drv.PrjPcb create Fabrication.OutJob containing: Gerber X2 (all used layers), NC Drill (mm, 2:5), ODB++, ActiveBOM-based BOM (CSV, columns per docs/bom_template.csv), Pick and Place (CSV, mm), and Assembly Drawings PDF (top/bottom). Map outputs to a container writing to Project Outputs/Rev_B and generate them.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clicktype· Text & formsnav· Pan/zoom/scroll- Work product
WP09· Files & folders- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Parse .OutJob: 6 output types with stated settings and container path; generated folder holds Gerber X2 set (XOR vs reference < 0.1%), drill with 2:5 mm format, ODB++ tgz, BOM columns equal template, P&P row count = placed parts, PDF with 2 pages. Scripting disabled.
Proposed partial credit
30% OutJob outputs configured; 30% fab files correct; 25% BOM/P&P; 15% assembly PDF
R07.03.02.03-T10 Create an Altium library component with an IPC-wizard QFN footprint
Original instruction
In fixtures/libs/Company.LibPkg add component STM32G031K8U6: schematic symbol from docs/stm32g031_pinout.pdf (UFQFPN32), footprint generated with the IPC Compliant Footprint Wizard (5×5 mm, 0.5 mm pitch, 3.5 mm EP, density level N), and parameters Manufacturer, MPN, Datasheet. Compile the library with 0 errors and place the part in test.SchDoc.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
type· Text & formsclick· Point & clickgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Exported ASCII lib: 33 pins with names per pinout; footprint pads positions/sizes within 0.01 mm of IPC-7351B nominal; EP 3.5 mm; courtyard present; 3 parameters set; library compile report 0 errors; component placed. Scripting disabled.
Proposed partial credit
35% symbol pins; 35% footprint geometry; 15% parameters; 15% compile & placement
R07.03.02.03-T11 Correct a transistor pin mapping error found at bring-up and rework the board
Original instruction
Bring-up note docs/bringup_q2.txt says Q2 (MMBT3904) was assembled with base and emitter swapped. In fixtures/relay_ctl/relay_ctl.kicad_pro determine from docs/mmbt3904.pdf whether the symbol pin mapping or footprint is wrong, fix it in the project library (not the global one), update PCB, reroute Q2's nets, pass ERC/DRC, and bump the board revision text to Rev C.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickpath· Continuous pathvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Project-local lib fixed (pin numbers B=1, E=2, C=3 per SOT-23 datasheet); global lib unchanged; PCB nets on Q2 pads match datasheet; Q2 nets routed; ERC/DRC 0 errors; title block and silk text show 'Rev C'.
Proposed partial credit
35% correct root cause fixed in project lib; 30% PCB updated & rerouted; 20% DRC/ERC clean; 15% revision text
R07.03.02.03-T12 Mark DNP parts for a lite variant and export a variant-correct BOM
Original instruction
docs/variant_lite.xlsx lists 6 parts to omit in the Lite build of fixtures/gateway/gateway.kicad_pro. Set Do Not Populate on those parts in the schematic (not by deleting), regenerate a BOM CSV excluding DNP parts and a position file excluding them. Save the project.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad · Excel
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickmulti· Cross-app- Work product
WP02· Records/table- Conditions
multiapp· Multi-app- Proposed difficulty
- 2 / 5
Proposed verifier
Schematic: exactly the 6 parts have dnp=yes, part count unchanged; BOM excludes them (row/qty totals match key); position file has N-6 rows. Deleting parts or editing BOM CSV by hand fails the schematic check.
Proposed partial credit
50% DNP flags exact; 25% BOM; 25% position file
R07.03.02.03-T13 Panelize a board 2×3 with mouse bites, rails and fiducials using KiKit
Original instruction
Using KiKit and kicad-cli, panelize fixtures/badge/badge.kicad_pcb as a 2×3 grid with 2 mm spacing, mouse-bite tabs (0.5 mm holes, 0.8 mm pitch, 3 tabs per long edge), 5 mm top/bottom rails with 3 fiducials and 4 NPTH 3.0 mm tooling holes. Save out/panel.kicad_pcb and export its Gerbers to out/panel_gerbers/. Put the command in out/panel.sh.
- Platforms
lin· Linuxmac· macOS- Applications
- kicad-cli · KiKit
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parse panel board: 6 board instances on 2×3 grid with 2±0.01 mm gaps; tab holes 0.5 mm at 0.8 mm pitch; rails 5 mm; 3 fiducials, 4 NPTH 3.0 mm; DRC 0 errors; Gerbers present; panel.sh reproduces identical output.
Proposed partial credit
30% grid & spacing; 25% tabs; 25% rails/fiducials/tooling; 20% Gerbers + script
R07.03.02.03-T14 Make a project self-contained by moving all symbols, footprints and 3D models local
Original instruction
fixtures/drone_fc/drone_fc.kicad_pro depends on 3 global libraries and absolute 3D-model paths on a former engineer's machine. Create project libraries drone_fc.kicad_sym and drone_fc.pretty containing every used symbol/footprint, update project sym-lib-table/fp-lib-table, repoint all references, copy 3D models into 3d/ referenced via ${KIPRJMOD}. ERC/DRC must stay unchanged.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formscode· Code & commands- Work product
WP09· Files & folders- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Open project in a clean container with no global libs: 0 missing symbols/footprints/3D models (kicad-cli export step logs no missing model); all lib_ids use 'drone_fc:' nickname; all model paths start ${KIPRJMOD}/3d; ERC/DRC counts equal fixture baseline.
Proposed partial credit
35% symbols local; 35% footprints local; 20% 3D models relative; 10% ERC/DRC unchanged
R07.03.02.03-T15 Find two opens reported by the fab's netlist test and fix them
Original instruction
The fab's electrical-test report docs/fab_et_report.txt lists 2 opens against IPC-D-356 for fixtures/sdr/sdr.kicad_pcb. Export a fresh IPC-D-356, compare it with the fab's netlist in docs/fab_netlist.ipc, locate both opens on the board (e.g. a zone not filled, a stub), fix them in KiCad, rerun DRC and regenerate IPC-D-356 and Gerbers to out/.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad · kicad-cli
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commandsvis· Visual judgmentpath· Continuous path- Work product
WP06· Code/engineering- Conditions
hidden· Hidden/stale state- Proposed difficulty
- 4 / 5
Proposed verifier
New IPC-D-356 connectivity equals schematic netlist (0 opens/shorts); the two seeded defects fixed (zone refilled, stub connected); DRC 0 unconnected; Gerbers regenerated and XOR vs reference differs only at defect sites.
Proposed partial credit
30% both opens identified (out/findings.txt); 40% both fixed; 15% DRC clean; 15% outputs regenerated
R07.03.02.03-T16 Swap MCU GPIO pins in layout and back-annotate the swap to the schematic
Original instruction
In fixtures/keypad/keypad.kicad_pcb the row lines ROW0-ROW3 cross badly at U1. Per docs/pin_swap_allowed.csv (which pins are interchangeable), swap the four row nets between allowed U1 pins to remove all crossings, update the schematic so labels follow the swap, reroute the rows and save both files with DRC/ERC clean.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickpath· Continuous pathvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
PCB and schematic netlists equal (Update PCB dry-run 0 changes); each ROW net on an allowed pin; routed ROW tracks have 0 self-crossings via layer change count ≤ fixture-2; ERC/DRC 0 errors; firmware pin map out/pinmap.h matches. KiCad Python console and IPC API disabled; writes to .kicad_sch/.kicad_pcb by any process other than KiCad are flagged by a file audit log.
Proposed partial credit
30% legal pin swaps; 30% schematic back-annotated; 25% rerouted with fewer vias; 15% pinmap.h
R07.03.02.03-T17 Replace an obsolete part across an Altium project via ActiveBOM
Original instruction
fixtures/power_mon/power_mon.PrjPcb uses INA219AIDR in 3 places; it is marked obsolete. In ActiveBOM pick the alternative INA219BIDR from the Manufacturer Part Search panel, update all three instances (same footprint), regenerate the BOM per Fabrication.OutJob and save. Footprints and PCB must remain unchanged.
- Platforms
win· Windows- Applications
- Altium
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clicktype· Text & forms- Work product
WP02· Records/table- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
Exported BOM shows INA219BIDR qty 3 and no INA219AIDR; .BomDoc has the solution attached; schematic parameters updated on all 3; PCB ASCII diff vs fixture empty except parameter fields. Scripting disabled.
Proposed partial credit
40% three instances updated; 30% BOM regenerated; 30% PCB unchanged
R07.03.02.03-T18 Import an Altium project into KiCad and reproduce matching fab outputs
Original instruction
Import fixtures/legacy_ad/ctrl.PrjPcb into KiCad 9 (schematic and PCB). Fix import issues listed by the importer (unmapped layers, broken polygons, missing footprints, net-tie handling) so that ERC/DRC are clean, then export Gerbers and drill to out/. They must match the Altium-generated reference set in fixtures/legacy_ad/ref_gerbers/.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad · kicad-cli
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickvis· Visual judgmentcode· Code & commands- Work product
WP06· Code/engineering- Conditions
long· Long-horizonmultiapp· Multi-app- Proposed difficulty
- 5 / 5
Proposed verifier
Gerber XOR per layer vs Altium reference ≤0.2% pixels at 2 mil resolution; drill hits identical (position ±0.01 mm, sizes); KiCad netlist equals Altium netlist (name-normalized); ERC/DRC 0 errors.
Proposed partial credit
25% project imports and opens; 25% netlist equivalence; 35% per-layer Gerber match (scaled); 15% drill match
R07.03.02.03-T19 Bring a board to a fab's DFM limits, fix violations and release outputs
Original instruction
Target fab capability is in docs/fab_caps_2layer.pdf (min trace/space 0.127 mm, min drill 0.3 mm, annular ring 0.13 mm, mask sliver 0.1 mm, silk-to-pad 0.15 mm). In fixtures/iot_node/iot_node.kicad_pro set Board Setup constraints to these values, run DRC, fix every violation without changing the netlist, and export Gerbers, drill, BOM and CPL to out/release_A/.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad · kicad-cli
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
type· Text & formspath· Continuous pathvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Board constraints equal spec; DRC with those constraints 0 errors/0 unconnected; netlist unchanged; independent DFM check (gerber-based min width/space/drill/ring) passes; release folder complete.
Proposed partial credit
15% constraints set; 45% violations fixed (scaled by count); 20% independent DFM pass; 20% release outputs
R07.03.02.03-T20 Import a vendor footprint/symbol zip, fix a pad mismatch and assign it
Original instruction
fixtures/vendor/LIS3DH_ultralibrarian.zip contains KiCad symbol and footprint for U6 in fixtures/imu/imu.kicad_pro. Add them to the project libraries, fix the footprint where pad numbers 13-16 are rotated relative to the datasheet (docs/lis3dh.pdf), assign to U6 and update the PCB.
- Platforms
mac· macOSwin· Windows- Applications
- KiCad
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Project libs contain the parts; footprint pad numbers/positions match datasheet (all 16 pads); U6 uses it; PCB pads on correct nets after update; ERC 0 errors.
Proposed partial credit
25% libs imported; 45% pad numbering corrected; 30% assigned & PCB updated
Mapped research references
Existing benchmark-to-class links from the research catalog. They are not record-level annotations, executions or product endorsements.