RTL-to-GDS flow & signoff
Configure synthesis, place-and-route and signoff to meet timing and area.
20 project-authored proposals · taxonomy v1.1 · 0 new benchmark runs. Verifiers and partial-credit rules below are designs, not executed results.
- Typical applications
- OpenROAD · Yosys · Innovus (Tcl)
- Class GUI-need label
CL· CLI-sufficient
Task proposals · 20
Expand to inspect the complete original wording and proposed checks. Original proposal text remains English in both interfaces.
R07.04.01.02-T01 Tune ORFS config for ibex on sky130hd to pass DRC, LVS and setup timing
Original instruction
In OpenROAD-flow-scripts, designs/sky130hd/ibex/config.mk fails at 10.0 ns (setup WNS -1.2 ns, 37 DRT violations). Edit only config.mk and constraint.sdc knobs other than the clock period (utilization, place density, synth flags, CTS/GRT settings) so a full make passes final DRC, LVS and setup/hold WNS ≥0 at 10.0 ns with power ≤ the baseline. Record each attempt in JOURNAL.md.
- Platforms
lin· Linux- Applications
- OpenROAD · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 4 / 5
Proposed verifier
Grader reruns make from clean with the submitted config using its own golden SDC clock (10.0 ns): Magic DRC 0, netgen LVS match, OpenSTA setup and hold WNS ≥0, total power ≤ baseline. Clock-period edits, removing constraints or editing scripts outside config.mk cause 0.
Proposed partial credit
25% DRC clean; 25% LVS match; 30% setup/hold met; 20% power ≤ baseline & journal
R07.04.01.02-T02 Run ORFS floorplan at 45% utilization and report die and core area
Original instruction
For designs/sky130hd/gcd in OpenROAD-flow-scripts set CORE_UTILIZATION=45, CORE_ASPECT_RATIO=1 and CORE_MARGIN=2, run through floorplan only, and write out/area.json with die_area_um2 and core_area_um2 read from the floorplan ODB.
- Platforms
lin· Linux- Applications
- OpenROAD
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP12· Answer/decision- Conditions
- None declared
- Proposed difficulty
- 1 / 5
Proposed verifier
Grader opens 2_floorplan.odb: core aspect 1.00±0.02, util 45±1%; area.json values within 0.5% of ODB-derived values.
Proposed partial credit
50% floorplan with right knobs; 50% correct areas reported
R07.04.01.02-T03 Synthesize PicoRV32 to sky130 with Yosys under an area target
Original instruction
Write synth.ys that reads rtl/picorv32.v (top picorv32), synthesizes to sky130_fd_sc_hd tt_025C_1v80 liberty with ABC area optimization, and writes out/picorv32_syn.v and out/stat.txt. Total cell area must be ≤ 1.10× the reference in docs/area_ref.txt and the netlist must be equivalent to RTL.
- Platforms
lin· Linuxmac· macOS- Applications
- Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Grader reruns synth.ys; parses stat for chip area ≤1.10× reference; only liberty cells used; eqy/SymbiYosys equivalence RTL vs netlist PASS.
Proposed partial credit
30% script runs & maps to liberty; 40% area target; 30% equivalence pass
R07.04.01.02-T04 Write SDC for a two-clock design with async crossing and IO budgets
Original instruction
rtl/dual_clk_top.v has clk_a (100 MHz) and clk_b (66.7 MHz) with a synchronizer between them. Write constraint.sdc: both clocks, 0.1 ns uncertainty, input/output delays at 40% of the respective period relative to the right clock, asynchronous clock groups, and set_max_delay -datapath_only for the synchronizer first flops. OpenSTA must report no unconstrained endpoints.
- Platforms
lin· Linux- Applications
- OpenROAD · OpenSTA
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
OpenSTA on provided netlist: check_setup -unconstrained_endpoints empty; clocks/periods match; IO delays per port ±0.01 ns; clock groups async; max_delay on sync paths only (grader compares path groups to key).
Proposed partial credit
25% clocks; 25% IO delays; 25% async groups/max_delay; 25% no unconstrained endpoints
R07.04.01.02-T05 Repair post-CTS hold violations without breaking setup
Original instruction
fixtures/aes_cts/4_cts.odb (sky130hd) has 212 hold violations (WNS -0.18 ns) after CTS. In OpenROAD use repair_timing -hold with an appropriate margin and buffer list, then re-legalize and save 4_cts_fixed.odb. Setup WNS must not drop below 0 and inserted buffer count must stay ≤600.
- Platforms
lin· Linux- Applications
- OpenROAD
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader loads ODB with golden SDC: hold WNS ≥0 and TNS 0; setup WNS ≥0; inserted hold buffers ≤600; check_placement clean.
Proposed partial credit
45% hold met; 25% setup preserved; 15% buffer budget; 15% legal placement
R07.04.01.02-T06 Resolve detailed-routing congestion overflow with density and macro halos
Original instruction
designs/sky130hd/jpeg in ORFS finishes with 1,480 DRT violations caused by congestion near two macros. Change only placement density, macro halo/channel settings and global-route layer adjustments in config.mk so detailed routing ends with 0 violations, timing at the given clock unchanged (WNS ≥0).
- Platforms
lin· Linux- Applications
- OpenROAD
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 4 / 5
Proposed verifier
Clean rerun: 5_route DRC report 0 violations; GRT overflow 0; setup WNS ≥0 with golden SDC; diff of config.mk limited to allowed variables.
Proposed partial credit
50% DRT violations reduced (scaled to 0); 20% GRT overflow 0; 20% timing; 10% allowed knobs only
R07.04.01.02-T07 Place four SRAM macros and build a PDN that connects them
Original instruction
designs/sky130hd/soc_lite has four sky130_sram_2kbyte macros. Write macro_placement.tcl (positions, R0/MX orientations, pins facing core logic, ≥20 µm channels) and a custom pdn.tcl so macro VDD/VSS pins connect to met4/met5 straps. Run ORFS to final; DRC, LVS and setup at 25 ns must pass.
- Platforms
lin· Linux- Applications
- OpenROAD · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Final ODB: macros at legal non-overlapping positions with ≥20 µm channels and pins facing core centroid; check_power_grid passes for VDD/VSS (no unconnected macro pins); DRC 0; LVS match; WNS ≥0.
Proposed partial credit
25% legal macro placement; 25% PDN connectivity; 20% DRC; 30% LVS & timing
R07.04.01.02-T08 Implement a block in Innovus by Tcl to meet 500 MHz
Original instruction
Using Cadence Innovus 21 batch Tcl with the provided LEF/LIB/QRC (gpdk045), implement fixtures/fir16/fir16_syn.v: floorplan at 70% util, power rings and M7/M8 stripes, place_opt_design, ccopt_design, route, postRoute optimization. Constraints in fir16.sdc (2.0 ns). Save fir16_final.enc and stream out GDS.
- Platforms
lin· Linux- Applications
- Innovus (Tcl)
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Grader restores DB and runs timeDesign -postRoute with golden SDC: setup/hold WNS ≥0; verify_drc 0; verify_connectivity 0 opens; PG rings/stripes present; GDS streams. SDC modifications ignored.
Proposed partial credit
35% floorplan+PG, placed & CTS; 20% routed DRC-clean; 30% timing met; 15% GDS out
R07.04.01.02-T09 Implement a metal-only ECO with spare cells and prove it with LEC
Original instruction
A logic bug in fixtures/uart_ctrl requires inverting the enable of the TX FIFO (docs/eco_req.txt; golden RTL rtl_v2/). Starting from the routed Innovus database, implement the fix using only existing spare cells (no base-layer change), ECO-route, and run Conformal LEC against rtl_v2 to prove equivalence.
- Platforms
lin· Linux- Applications
- Innovus (Tcl) · Conformal LEC
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 5 / 5
Proposed verifier
Base layers (FEOL+contacts) XOR vs original GDS empty; LEC vs rtl_v2 EQUIVALENT; verify_drc 0; timing WNS ≥0; only spare instances re-connected.
Proposed partial credit
30% FEOL unchanged; 40% LEC equivalent; 15% DRC; 15% timing
R07.04.01.02-T10 Find a seeded mismatch between RTL and gate netlist with equivalence checking
Original instruction
fixtures/alu32 has RTL and a hand-patched gate netlist alu32_syn.v that differs functionally in one cone. Set up an eqy (Yosys) equivalence check, identify the failing output and the netlist instance responsible, fix the netlist and show equivalence passes. Write the instance name to out/culprit.txt.
- Platforms
lin· Linuxmac· macOS- Applications
- Yosys · eqy
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
culprit.txt equals seeded instance; grader's own eqy on the fixed netlist PASS; diff vs original confined to that instance's connections.
Proposed partial credit
30% eqy setup reports failure; 30% culprit correct; 40% fixed & equivalent
R07.04.01.02-T11 Use the OpenROAD GUI timing and heatmap views to fix a critical-path bottleneck
Original instruction
fixtures/riscv_mini/3_place.odb misses setup by 0.4 ns. Open it in the OpenROAD GUI, use the Timing Report and placement-density/RUDY heatmaps to find why the critical path is spread out, then fix it (e.g. region constraints, buffering, resizing) via Tcl and write 3_place_fixed.odb with WNS ≥0. Save a GUI screenshot of the path to out/path.png and describe the cause in out/cause.txt.
- Platforms
lin· Linux- Applications
- OpenROAD
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
HY· Hybrid- Interaction primitives
vis· Visual judgmentnav· Pan/zoom/scrollcode· Code & commands- Work product
WP06· Code/engineering- Conditions
multiapp· Multi-app- Proposed difficulty
- 4 / 5
Proposed verifier
Grader: setup WNS ≥0 with golden SDC; legal placement; cause.txt names the start/end registers and spread cause matching key (string match + VLM check of screenshot showing highlighted path).
Proposed partial credit
20% correct path identified; 20% cause; 50% WNS ≥0 legal; 10% screenshot
R07.04.01.02-T12 Reduce worst static IR drop below 5% by strengthening the PDN
Original instruction
OpenROAD analyze_power_grid on fixtures/dsp_core/5_route.odb reports worst VDD IR drop 9.1% at 1.8 V. Edit pdn.tcl (strap pitch/width/layers) and rerun the flow from floorplan so worst static IR drop is ≤5% while final DRC stays 0 and timing is met. Write the before/after report to out/ir.txt.
- Platforms
lin· Linux- Applications
- OpenROAD
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP07· Simulation result- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader reruns analyze_power_grid with fixed current file: worst drop ≤5%; DRC 0; LVS match; WNS ≥0; routing-track loss reported.
Proposed partial credit
50% IR drop at target (scaled from the 9.1 pct baseline); 20% DRC; 15% LVS; 15% timing
R07.04.01.02-T13 Fix an LVS failure caused by missing tap and fill cells in signoff
Original instruction
ORFS final GDS for designs/sky130hd/spm passes DRC but netgen LVS fails because tapcell and fill insertion were skipped and a power net is split. Locate the cause in the logs, fix config/scripts, rerun from the right stage, and get Magic DRC 0 and netgen LVS match.
- Platforms
lin· Linux- Applications
- OpenROAD · Magic · netgen
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
hidden· Hidden/stale state- Proposed difficulty
- 3 / 5
Proposed verifier
Final GDS: tap cells per row spacing rule, fill present; Magic DRC 0; netgen LVS 'Circuits match uniquely'; note in out/root_cause.txt matches key.
Proposed partial credit
25% root cause; 25% taps/fill inserted; 25% DRC; 25% LVS
R07.04.01.02-T14 Find a design's maximum clock frequency by sweeping the period
Original instruction
For designs/sky130hd/aes in ORFS, find the smallest clock period (0.1 ns resolution) for which the full flow ends with setup WNS ≥0 and DRC 0, using a sweep script that runs flows in parallel. Write out/fmax.json with period_ns and fmax_mhz plus the script.
- Platforms
lin· Linux- Applications
- OpenROAD · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP12· Answer/decision- Conditions
long· Long-horizon- Proposed difficulty
- 3 / 5
Proposed verifier
Grader reruns at reported period (must pass) and at period-0.1 ns (must fail); fmax_mhz = 1000/period within 0.5%.
Proposed partial credit
30% sweep script runs; 40% reported period passes; 30% period-0.1 fails
R07.04.01.02-T15 Harden a Caravel user project with OpenLane 2 so precheck passes
Original instruction
fixtures/caravel_user/ contains RTL for a 16-bit PWM block. Write openlane/user_proj_pwm/config.json (fixed DIE_AREA from docs, pin order file per wishbone/IO spec, clock 40 ns), harden with OpenLane 2, integrate into user_project_wrapper and run the mpw_precheck subset in docs/precheck.md.
- Platforms
lin· Linux- Applications
- OpenLane · OpenROAD · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
tutorial· Follow docs/tutorial- Proposed difficulty
- 3 / 5
Proposed verifier
OpenLane run final: DRC 0, LVS clean, antenna 0, WNS ≥0; pins on edges per order file; wrapper GDS present; precheck subset returns all PASS.
Proposed partial credit
25% config & pin order; 30% harden signoff clean; 20% wrapper integration; 25% precheck pass
R07.04.01.02-T16 Write a Yosys flow with dont_use cells, flattening and retiming
Original instruction
Create synth_retime.ys for rtl/fir8.v targeting fixtures/lib/acme45_tt.lib: flatten, honor dont_use on all *_X16 and CLKBUF* cells, enable ABC with -dff retiming, and map flops to DFFR_X1 only. Output out/fir8_syn.v and out/stat.txt.
- Platforms
lin· Linuxmac· macOS- Applications
- Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Netlist flat (single module); no dont_use cells instantiated; all sequential cells DFFR_X1; sequential equivalence (SymbiYosys BMC depth 20) vs RTL passes; OpenSTA worst path shorter than non-retimed baseline.
Proposed partial credit
35% flat & flop mapping; 25% dont_use honored; 25% equivalent; 15% timing improved
R07.04.01.02-T17 Place IO pins by group and order with OpenROAD place_pins
Original instruction
For fixtures/spi_bridge/2_floorplan.odb place pins with OpenROAD: SPI pins on the left edge in order sclk, mosi, miso, cs_n; data_out[15:0] on the right edge ascending top to bottom; clk and rst_n on the bottom; met3 horizontal, met2 vertical, min distance 5 tracks. Save 2_pins.odb.
- Platforms
lin· Linux- Applications
- OpenROAD
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Read ODB: each pin on required edge and layer; ordering constraints satisfied; spacing ≥5 tracks; no overlaps.
Proposed partial credit
40% edges correct; 30% ordering; 15% layers; 15% spacing
R07.04.01.02-T18 Route clock nets with a double-width double-spacing non-default rule
Original instruction
On fixtures/mac16/4_cts.odb define an NDR CLK_2W2S (2× width, 2× spacing on met2-met4), assign it to all clock nets, run global and detailed routing in OpenROAD and save 5_route.odb. Detailed-route violations must be 0.
- Platforms
lin· Linux- Applications
- OpenROAD
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
ODB: NDR exists with 2× values; every clock net references it and routed wires on met2-met4 have ≥2× min width; DRT 0 violations; non-clock nets use default rule.
Proposed partial credit
25% NDR defined; 25% assigned to clock nets; 30% routed widths; 20% DRC clean
R07.04.01.02-T19 Shrink core area by 15% while keeping timing and routability
Original instruction
designs/sky130hd/ibex currently closes at CORE_UTILIZATION 35. Reduce core area by ≥15% versus baseline (docs/baseline.json) by changing utilization, synthesis area recipes or buffering limits, while final DRC is 0, LVS matches and setup/hold WNS ≥0 at the original clock. Report area in out/area.json.
- Platforms
lin· Linux- Applications
- OpenROAD · Yosys
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 4 / 5
Proposed verifier
Grader reruns: core area ≤0.85× baseline; DRC 0; LVS match; WNS ≥0 with golden SDC; area.json correct.
Proposed partial credit
40% area reduction (scaled to target); 20% DRC; 15% LVS; 25% timing
R07.04.01.02-T20 Diagnose a failed CTS stage from logs and resume the flow
Original instruction
An ORFS run of designs/sky130hd/uart stopped at CTS with an error (logs in fixtures/uart_logs/). Find the root cause (an invalid CTS_BUF_CELL list for the platform), correct config.mk, rerun from CTS without redoing synthesis/floorplan, and finish to a clean final report.
- Platforms
lin· Linux- Applications
- OpenROAD
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Final ODB exists with DRC 0 and WNS ≥0; 1_synth.v and 2_floorplan.odb timestamps unchanged (resumed, not rerun); config.mk CTS buffer list valid for sky130hd.
Proposed partial credit
30% root cause in out/notes.txt; 30% config fixed; 20% resumed from CTS; 20% clean final
Mapped research references
Existing benchmark-to-class links from the research catalog. They are not record-level annotations, executions or product endorsements.