FPGA build & timing closure
Assemble IP block designs, constraints and close timing in vendor tools.
20 project-authored proposals · taxonomy v1.1 · 0 new benchmark runs. Verifiers and partial-credit rules below are designs, not executed results.
- Typical applications
- Vivado · Quartus Prime · Radiant
- Class GUI-need label
HY· Hybrid
Task proposals · 20
Expand to inspect the complete original wording and proposed checks. Original proposal text remains English in both interfaces.
R07.04.01.03-T01 Build a Zynq block design with AXI GPIO driving four LEDs and export the XSA
Original instruction
In Vivado 2024.2 create project zynq_leds for the PYNQ-Z2 board (xc7z020clg400-1). In IP Integrator add the Zynq PS (board preset), an AXI GPIO (4-bit output, board interface leds_4bits), run connection automation, validate, create the HDL wrapper, generate the bitstream with WNS ≥0 and export hardware including bitstream to out/zynq_leds.xsa.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parse .bd JSON: processing_system7 + axi_gpio (C_GPIO_WIDTH=4, all outputs) connected via interconnect; address map assigned; validate_bd_design clean in batch; routed DCP timing WNS ≥0; XSA contains .bit and hwh. Journal checked for completion of all steps.
Proposed partial credit
35% block design correct; 15% validation clean; 30% bitstream with timing met; 20% XSA exported
R07.04.01.03-T02 Assign eight I/O with Pin Planner on a DE10-Lite and compile
Original instruction
Open fixtures/de10_counter/de10_counter.qpf in Quartus Prime Lite 23.1. Using Pin Planner, assign CLOCK_50, KEY[1:0] and LEDR[4:0] to the pins in docs/DE10-Lite_manual.pdf (table 3-x) with 3.3-V LVTTL standard. Compile and save.
- Platforms
win· Windowslin· Linux- Applications
- Quartus Prime
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
.qsf contains exactly 8 location assignments matching the key and IO_STANDARD 3.3-V LVTTL for each; no extra pin assignments; compile succeeds (fit report shows those pins).
Proposed partial credit
60% correct pin locations (7.5 pts each); 20% IO standards; 20% compile success
R07.04.01.03-T03 Constrain a 200 MHz clock and pipeline the critical path until timing closes
Original instruction
fixtures/mac_unit (Vivado, xc7a100t) fails at 200 MHz with WNS -1.9 ns through a 32×32 multiply-add. Add a 5.0 ns create_clock in constraints.xdc, then pipeline the RTL (add ≤3 register stages, use DSP48 MREG/PREG) keeping the cycle-accurate behavior described by the new latency in docs/spec.md. Implement with WNS ≥0 and pass the provided testbench.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commandsclick· Point & clickvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader implements with its golden XDC (5.0 ns): WNS ≥0, WHS ≥0; testbench with expected latency passes in xsim; DSP48 utilization uses internal pipeline registers; ≤3 added stages.
Proposed partial credit
10% clock constrained; 40% timing met; 35% testbench passes; 15% DSP pipelining used
R07.04.01.03-T04 Clear CDC critical warnings with XPM synchronizers and datapath constraints
Original instruction
fixtures/cam_bridge (Vivado, xczu3eg) has 3 clock domains; report_cdc shows 14 Critical (CDC-1, CDC-4, CDC-10). Insert xpm_cdc_single / xpm_cdc_gray / xpm_cdc_handshake as appropriate in RTL, add set_max_delay -datapath_only only where justified, and get report_cdc to 0 Critical with timing met. Explain each fix in out/cdc_fixes.md.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commandsvis· Visual judgmentclick· Point & click- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader reruns synth/impl: report_cdc 0 Critical; no blanket set_false_path between clocks; max_delay only on XPM-internal paths; WNS/WHS ≥0; existing testbench still passes.
Proposed partial credit
45% CDC criticals cleared (scaled); 20% no blanket false paths; 20% timing; 15% testbench
R07.04.01.03-T05 Configure an MMCM with three output clocks via Clocking Wizard
Original instruction
In fixtures/eth_cam (Vivado, Arty A7-100) add a Clocking Wizard IP: 100 MHz input, outputs 125 MHz, 200 MHz and 25 MHz (0° phase), reset active-low, locked output. Instantiate it in top.v, drive the three existing clock domains from it, regenerate output products and implement with timing met.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
.xci parameters: CLKOUT1/2/3 requested and actual frequencies 125/200/25 MHz ±0.1%; RESET_TYPE ACTIVE_LOW; LOCKED enabled; netlist clocks of the 3 domains driven by MMCM outputs; WNS/WHS ≥0.
Proposed partial credit
40% IP configuration; 30% instantiated & wired; 30% timing met
R07.04.01.03-T06 Assemble a Nios V system in Platform Designer and simulate a boot
Original instruction
In Quartus Prime Lite 23.1 for MAX 10 (10M50DAF484C7G), create Platform Designer system soc.qsys: Nios V/m, 64 KB on-chip RAM initialised from fixtures/hello.hex, JTAG UART, 8-bit PIO output. Assign base addresses without overlap, generate HDL and a simulation model, compile, and run the provided Questa testbench showing PIO = 0xA5.
- Platforms
win· Windowslin· Linux- Applications
- Quartus Prime · Questa
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
multiapp· Multi-app- Proposed difficulty
- 4 / 5
Proposed verifier
Parse .qsys: 4 components with stated params and connections; no address overlaps; RAM init file set; compile succeeds; grader runs testbench: PIO output 0xA5 within 200 µs sim time.
Proposed partial credit
35% system composed; 15% addresses; 20% compile; 30% simulation shows 0xA5
R07.04.01.03-T07 Constrain pins and a 48 MHz clock in Lattice Radiant and build a bitstream
Original instruction
Open fixtures/ice_blink/ice_blink.rdf in Lattice Radiant 2024.1 for iCE40UP5K-SG48. Using the Device Constraint Editor assign clk to pin 35, led_r/g/b to pins 39/40/41 (LVCMOS33), add a 48 MHz create_clock in the PDC, and export the bitstream.
- Platforms
win· Windowslin· Linux- Applications
- Radiant
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
PDC contains 4 ldc_set_location entries and IO_TYPE LVCMOS33; create_clock period 20.833 ns; bitstream .bin exists; timing report shows constraint met.
Proposed partial credit
50% pin locations; 20% IO type; 15% clock constraint; 15% bitstream
R07.04.01.03-T08 Insert an ILA on three nets with a trigger and generate debug probes
Original instruction
In fixtures/spi_master (Vivado, Basys 3) synthesize, open Set Up Debug, mark sclk, mosi and state[3:0] for debug, create an ILA with depth 4096 and input pipe stages 1 on clk_100, implement and write the bitstream and debug probes file. Save a trigger setup (state == 4'h3 rising) as out/trigger.tas.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicknav· Pan/zoom/scrolltype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Routed DCP contains ila core with depth 4096 and probe widths 1,1,4 connected to the named nets; .ltx lists those probes; trigger file condition state==3; timing met. XDC-based debug (manual create_debug_core lines) flagged by journal.
Proposed partial credit
40% ILA with correct probes; 15% depth/pipe; 25% bitstream + ltx; 20% trigger setup
R07.04.01.03-T09 Set up a DFX partial-reconfiguration design with two RMs and partial bitstreams
Original instruction
fixtures/dfx_filters (Vivado, ZCU102) contains a static design and two filter modules (lpf, hpf) for region rp_filter. Enable Dynamic Function eXchange, create the partition definition, draw a Pblock for the RP sized to ≤1.3× resources, define two configurations, implement both and generate full and partial bitstreams. pr_verify must pass.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickgeom· Precise geometrynav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Project has partition def with 2 RMs and 2 configurations; Pblock contains RP with SNAPPING_MODE on and utilization 1/1.3-1 of capacity; both runs WNS ≥0; pr_verify PASS; 2 partial .bit files plus full.
Proposed partial credit
20% DFX partition set; 25% Pblock sized/placed; 25% both configs implemented; 30% pr_verify & partial bitstreams
R07.04.01.03-T10 Close -0.6 ns timing with strategies, floorplanning and phys_opt only
Original instruction
fixtures/video_scaler (Vivado, xc7k325t) misses 6.4 ns timing (WNS -0.6 ns). Without changing RTL or the clock, close timing using implementation strategies, Pblocks, phys_opt_design and justified multicycle paths only from docs/allowed_mcp.txt. Write the final checkpoint and a log of attempts in out/closure.md.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
vis· Visual judgmentgeom· Precise geometrycode· Code & commands- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Grader re-times final DCP with golden XDC plus allowed MCPs only: WNS ≥0, WHS ≥0; RTL hash unchanged; any constraint not in allowed list invalidates; route_status 100%.
Proposed partial credit
60% WNS improvement scaled from -0.6 to 0; 15% hold met; 15% constraints legal; 10% closure log
R07.04.01.03-T11 Write SDC with PLL-derived clocks and IO constraints in Quartus Timing Analyzer
Original instruction
fixtures/adc_capture (Quartus, Cyclone V) uses a PLL generating 3 clocks and a source-synchronous ADC input. Write adc_capture.sdc: base 50 MHz clock, derive_pll_clocks, a virtual ADC clock, set_input_delay min/max from docs/adc_timing.pdf, and false paths for the async reset. Timing Analyzer must report no unconstrained paths and positive slack.
- Platforms
win· Windowslin· Linux- Applications
- Quartus Prime
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
type· Text & formsclick· Point & clickvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
quartus_sta batch: report_ucp empty; all setup/hold slacks ≥0; input delay values equal datasheet-derived key ±0.05 ns; virtual clock exists.
Proposed partial credit
25% clocks; 35% IO delays correct; 20% no unconstrained; 20% slack ≥0
R07.04.01.03-T12 Add a Signal Tap instance with a sequential trigger in Quartus
Original instruction
In fixtures/i2c_ctrl (Quartus Lite, DE10-Lite) create Signal Tap file stp1.stp: sample clock clk, nodes scl, sda, state[2:0], depth 4096, sequential trigger: state==3'd2 then sda falling. Enable it in the project, compile and confirm the .sof contains the instance.
- Platforms
win· Windowslin· Linux- Applications
- Quartus Prime
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickdrag· Drag & droptype· Text & forms- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Parse .stp XML: nodes and depth correct; trigger flow sequential with 2 stages as specified; .qsf references stp1.stp with ENABLE_SIGNALTAP ON; compile report lists Signal Tap instance. Quartus Tcl console and quartus_sh/quartus_stp scripting disabled; stp1.stp must be saved by the Signal Tap GUI, and writes to .stp/.qsf by other processes are flagged by a file audit log.
Proposed partial credit
35% nodes; 15% depth; 30% trigger sequence; 20% compiled in
R07.04.01.03-T13 Build an HLS FIR kernel at II=1 and integrate it into a Zynq block design
Original instruction
Implement a 32-tap FIR (coefficients fixtures/fir_coefs.txt, 16-bit fixed point) in Vitis HLS with AXI4-Stream in/out and AXI-Lite control at II=1, 200 MHz. Pass C/RTL cosimulation, export IP, add it to the block design in fixtures/zu_dma (Vivado, Ultra96-V2) between DMA MM2S/S2MM, and implement with timing met.
- Platforms
win· Windowslin· Linux- Applications
- Vivado · Vitis HLS
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commandsclick· Point & clickdrag· Drag & drop- Work product
WP06· Code/engineering- Conditions
multiapp· Multi-applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
HLS report: II=1, achieved clock ≤5 ns; cosim PASS with golden vectors; block design contains IP connected in DMA loop; validate clean; implementation WNS ≥0; grader runs PS-side xsim/QEMU test vectors match within 1 LSB.
Proposed partial credit
25% HLS II=1 & timing; 20% cosim; 25% integration; 30% implementation timing & vector match
R07.04.01.03-T14 Build an AXI DMA loopback block design with a correct address map
Original instruction
In Vivado for ZCU104 create a block design: Zynq UltraScale+ MPSoC (board preset), AXI DMA (no SG, 26-bit length), AXI4-Stream Data FIFO looping MM2S to S2MM, interrupts concatenated to pl_ps_irq0, HP0 port for data. Assign the address map, validate, generate bitstream with timing met, export XSA.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickdrag· Drag & dropnav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
.bd JSON: DMA params match; FIFO in loop; IRQs concatenated; DMA masters mapped to HP0 DDR range; validate clean; WNS ≥0; XSA exported.
Proposed partial credit
35% topology; 35% address map & IRQs; 20% timing; 10% XSA
R07.04.01.03-T15 Migrate a Cyclone IV design to Cyclone V and replace legacy PLL IP
Original instruction
fixtures/legacy_vga targets EP4CE22 with an ALTPLL. Retarget the project to 5CSEMA5F31C6 (DE1-SoC), replace ALTPLL with an Altera PLL IP keeping 25.175 MHz and 50 MHz outputs, regenerate IP, remap pins per docs/DE1-SoC_pins.csv, and compile with timing met.
- Platforms
win· Windowslin· Linux- Applications
- Quartus Prime
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsmulti· Cross-app- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
.qsf device 5CSEMA5F31C6; new PLL IP outputs 25.175±0.01 MHz and 50 MHz; no ALTPLL instances; pins equal CSV mapping; compile succeeds; quartus_sta slack ≥0.
Proposed partial credit
20% device retargeted; 30% PLL replaced correctly; 25% pins remapped; 25% compile & timing
R07.04.01.03-T16 Write a non-project-mode Vivado Tcl build script for an Arty A7 design
Original instruction
For fixtures/uart_echo (RTL + arty.xdc), write build.tcl for Vivado non-project batch mode: read sources, synth_design for xc7a35ticsg324-1L, opt/place/route, write_bitstream to out/uart_echo.bit, and write timing/utilization reports. Run it with vivado -mode batch.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Grader runs build.tcl in a clean dir: bitstream produced; part correct; timing summary WNS ≥0; reports exist; no project (.xpr) created.
Proposed partial credit
40% script runs to bitstream; 30% timing met; 30% reports
R07.04.01.03-T17 Plan LVDS ADC I/O in a single bank with correct standards and termination
Original instruction
fixtures/adc_lvds (Vivado, xc7k160t) needs a 14-bit DDR LVDS ADC (DCO, FCO, D0-D6 pairs). In the I/O Planning view assign all pairs to bank 16 using clock-capable pins for DCO/FCO, set IOSTANDARD LVDS_25 with DIFF_TERM TRUE, and keep VCCO consistent. Run report_drc and DRC must be clean for IO rules.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropclick· Point & clickvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
XDC: 9 differential pairs in bank 16; DCO/FCO on MRCC/SRCC P-side pins; LVDS_25 + DIFF_TERM TRUE; report_drc no IO errors; implementation succeeds. Vivado Tcl console and -mode batch/tcl disabled; pin constraints must appear in vivado.jou as I/O Planning view actions, and XDC writes by other processes are flagged by a file audit log.
Proposed partial credit
40% pairs in bank 16 legal; 20% clock-capable pins; 25% IO standards; 15% DRC/impl clean
R07.04.01.03-T18 Cut dynamic power by 15% using activity data and power-optimization options
Original instruction
fixtures/fft_engine (Vivado, xc7a200t) has a SAIF activity file sim/fft.saif. Run report_power with it, then reduce dynamic power by ≥15% via power_opt_design, BRAM enable gating in RTL, or clock enables, without breaking timing or the testbench. Save before/after power reports to out/.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commandsvis· Visual judgmentclick· Point & click- Work product
WP07· Simulation result- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader recomputes report_power with the SAIF on final DCP: dynamic power ≤0.85× baseline; WNS ≥0; testbench passes; reports present.
Proposed partial credit
15% baseline with SAIF; 50% reduction (scaled to target); 20% timing; 15% testbench
R07.04.01.03-T19 Generate a PLL module in Radiant IP Catalog for 48 MHz from 12 MHz
Original instruction
In fixtures/usb_dev (Lattice Radiant, iCE40UP5K) use IP Catalog to create pll48 (input 12 MHz, output 48 MHz, global buffer), instantiate it in top.v replacing the external 48 MHz input, update the PDC clock constraints, and build a bitstream with timing met.
- Platforms
win· Windowslin· Linux- Applications
- Radiant
- Interfaces
desk· Desktop GUI- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formscode· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
IP .ipx config: in 12 MHz, out 48 MHz achieved exactly; top uses pll48 output; PDC clock on PLL output; timing report met; bitstream exists.
Proposed partial credit
40% PLL configured; 25% instantiated; 15% constraints; 20% bitstream timing met
R07.04.01.03-T20 Rebuild with incremental implementation after a small RTL change
Original instruction
fixtures/pcie_bridge (Vivado) has a timing-closed routed reference checkpoint ref/routed.dcp. Apply the RTL patch in patches/fix_status_reg.diff, then run incremental implementation against the reference so that ≥95% of cells are reused and timing stays met. Save the new routed DCP and the incremental reuse report.
- Platforms
win· Windowslin· Linux- Applications
- Vivado
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
report_incremental_reuse: cell reuse ≥95%; patch applied (RTL hash); WNS/WHS ≥0; routed DCP present.
Proposed partial credit
20% patch applied; 40% cell reuse (scaled to the 95 pct target); 40% timing met
Mapped research references
No benchmark reference is assigned to this class in the current mapping.