Custom/analog IC schematic & layout
Draw transistor-level schematics and layouts that pass DRC and LVS.
20 project-authored proposals · taxonomy v1.1 · 0 new benchmark runs. Verifiers and partial-credit rules below are designs, not executed results.
- Typical applications
- Cadence Virtuoso · Magic · KLayout · Calibre
- Class GUI-need label
G3· GUI-only
Task proposals · 20
Expand to inspect the complete original wording and proposed checks. Original proposal text remains English in both interfaces.
R07.04.01.01-T01 Lay out a sky130 CMOS inverter in Magic that passes DRC and LVS
Original instruction
Schematic fixtures/inv/inv.sch (xschem) defines an inverter: nfet W=0.65 L=0.15, pfet W=1.3 L=0.15, pins A, Y, VPWR, VGND. In Magic with the sky130A tech file, draw layout inv.mag with poly gate, diffusions, contacts, n-well with tap, substrate tap and met1 pins labelled exactly as the schematic. Save inv.mag and write inv.gds.
- Platforms
lin· Linuxmac· macOS- Applications
- Magic
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
geom· Precise geometryclick· Point & clickkey· Shortcuts- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Batch magic -dnull: 'drc check' count 0 on inv.mag; ext2spice + netgen LVS vs xschem netlist: 'Circuits match uniquely'; device W/L equal schematic; 4 labelled ports. Magic Tcl 'source'/script files are blocked: session log must show interactive box/paint commands from the GUI (no batch script files in $HOME).
Proposed partial credit
30% devices with correct W/L; 30% DRC clean; 30% LVS match; 10% port labels
R07.04.01.01-T02 Fix five DRC errors in an OTA layout in KLayout without changing connectivity
Original instruction
fixtures/ota/ota.gds (sky130) has 5 DRC violations (poly spacing, li1 enclosure, met1 width, n-well spacing, contact enclosure) reported by the sky130 KLayout DRC deck. Fix all of them in KLayout by editing shapes only, keeping the netlist identical. Save ota_fixed.gds.
- Platforms
mac· macOSwin· Windowslin· Linux- Applications
- KLayout
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
geom· Precise geometryclick· Point & clicknav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Run sky130 KLayout DRC deck: 0 violations; KLayout LVS against ota.spice still matches; XOR vs fixture limited to boxes within 2 µm of the 5 marker locations. KLayout macro development (Ruby/Python) disabled; .lym files rejected.
Proposed partial credit
60% violations fixed (12 pts each); 30% LVS still clean; 10% edits localized
R07.04.01.01-T03 Draw and size a 5-transistor OTA in Virtuoso to meet gain and GBW
Original instruction
In Cadence Virtuoso (gpdk045) create library OTA_LIB with cell ota5t: schematic of an NMOS-input 5T OTA with tail current source, symbol, and testbench tb_ota with CL=1 pF, VDD=1.1 V. Using ADE Explorer, size devices so DC gain ≥40 dB, GBW ≥10 MHz, phase margin ≥60°, and total current ≤50 µA. Save the ADE state as ota_ac.
- Platforms
lin· Linux- Applications
- Cadence Virtuoso · Spectre
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickgeom· Precise geometrytype· Text & forms- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 4 / 5
Proposed verifier
Grader netlists tb_ota via si batch and reruns Spectre AC/DC: gain ≥40 dB, GBW ≥10 MHz, PM ≥60°, IDD ≤50 µA; schematic check-and-save 0 errors; symbol pins match schematic; ADE state ota_ac exists. SKILL CIW input disabled; cellview edit history must come from GUI sessions.
Proposed partial credit
35% schematic, symbol, testbench & state; 20% gain; 20% GBW; 25% PM & current
R07.04.01.01-T04 Lay out a common-centroid current mirror with dummies and guard ring in Layout XL
Original instruction
For cell mirror4 in fixtures/analog_lib (gpdk045; 4 matched NMOS of 8 fingers each), use Virtuoso Layout XL to generate from source and place fingers in an ABCD-DCBA common-centroid row pair, add dummy fingers at row ends, a P+ guard ring, and route with symmetric metal. Pass Calibre DRC and LVS and save layout.
- Platforms
lin· Linux- Applications
- Cadence Virtuoso · Calibre
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
geom· Precise geometrydrag· Drag & dropvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
Calibre DRC 0 results; Calibre LVS CORRECT; grader reads OA layout: finger centroid of each device within 0.05 µm of array center; ≥1 dummy per row end; closed P+ ring around array; per-device routed metal length difference ≤5%. SKILL disabled.
Proposed partial credit
40% CC placement, dummies & ring; 20% routing symmetry; 20% DRC clean; 20% LVS correct
R07.04.01.01-T05 Debug three LVS mismatches with Calibre RVE and fix them in the layout
Original instruction
Calibre LVS on fixtures/bias_gen (layout vs bias_gen.cdl) reports INCORRECT: one device with swapped source/drain naming effect, one missing substrate tie causing a floating bulk, and one short between VBN and VBP on met2. Use Calibre RVE highlighting in Virtuoso to locate each, fix the layout, rerun until CORRECT. Write fixes.txt listing each error and the fix location.
- Platforms
lin· Linux- Applications
- Calibre · Cadence Virtuoso
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickvis· Visual judgmentgeom· Precise geometry- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro apphidden· Hidden/stale state- Proposed difficulty
- 4 / 5
Proposed verifier
Calibre LVS CORRECT; Calibre DRC still 0; layout XOR vs fixture limited to ≤3 regions near seeded defects; fixes.txt names all three (keyword+coordinates within 2 µm). SKILL disabled.
Proposed partial credit
75% defects fixed (25 pts each); 10% DRC clean; 15% fixes.txt
R07.04.01.01-T06 Draw a bandgap reference in xschem and size it for low tempco
Original instruction
Reproduce the topology in docs/bandgap_fig.png in xschem with sky130 devices (PNP Q1/Q2 ratio 1:8, PMOS mirror, op-amp as provided subckt). Add a testbench sweeping temperature -40 to 125 °C at VDD=1.8 V and tune R1/R2 so Vref = 1.20±0.02 V with tempco ≤50 ppm/°C. Save schematics and write meas results to out/bg.log.
- Platforms
lin· Linuxmac· macOS- Applications
- xschem · ngspice
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropclick· Point & clickvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
Grader netlists with xschem -n -q and reruns ngspice: Vref(27 °C) 1.20±0.02 V; box tempco ≤50 ppm/°C; topology graph isomorphic to reference (device types and connections); hand-written .spice in place of .sch fails. xschem Tcl console and --script disabled; .sch files written by any process other than xschem are flagged by a file audit log.
Proposed partial credit
35% topology matches figure; 25% Vref; 30% tempco; 10% log written
R07.04.01.01-T07 Draw an interdigitated differential pair in KLayout and pass sky130 LVS
Original instruction
In KLayout with the sky130 PDK PCell library, lay out cell diffpair: two nfet devices W=4 L=0.5 split into 4 fingers each, interdigitated ABBAABBA with shared source, 2 dummies each side, tap ring, met1/met2 routing with equal lengths to D1/D2 pins. Save diffpair.gds; LVS against fixtures/diffpair.spice.
- Platforms
mac· macOSwin· Windowslin· Linux- Applications
- KLayout
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
geom· Precise geometrydrag· Drag & dropnav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 4 / 5
Proposed verifier
KLayout sky130 DRC 0; KLayout LVS match; finger order read from GDS equals ABBAABBA; dummies present; D1/D2 routed lengths differ ≤2%. Macros disabled; cell must contain PCell instances placed via GUI (no .lym in session).
Proposed partial credit
40% finger pattern, dummies & tap; 20% matched routing; 20% DRC; 20% LVS
R07.04.01.01-T08 Lay out a matched 4-bit resistor DAC with poly resistors in Magic
Original instruction
fixtures/rdac4/rdac4.sch is an R-2R ladder using sky130 high-res poly resistors (unit 10 kΩ). In Magic draw rdac4.mag with unit resistors in one row, dummy resistors at both ends, all R units same orientation, and switch transistors per schematic. Pass DRC and LVS and write a parasitic-extracted netlist out/rdac4_pex.spice.
- Platforms
lin· Linuxmac· macOS- Applications
- Magic · netgen
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
geom· Precise geometryclick· Point & clickvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
long· Long-horizon- Proposed difficulty
- 4 / 5
Proposed verifier
Magic DRC 0; netgen LVS unique match; unit resistors identical size/orientation (from extraction); dummies at ends; PEX netlist exists and ngspice INL of the 16 codes ≤0.25 LSB. Sourcing Tcl script files is blocked in Magic; grader checks Magic's command log for interactive paint/box edits.
Proposed partial credit
40% resistor array matched with dummies; 20% DRC; 20% LVS; 20% INL from PEX
R07.04.01.01-T09 Create a symbol view for an existing Virtuoso schematic to a pin-placement spec
Original instruction
Library ADC_LIB cell sar_logic has a schematic but no symbol. In Virtuoso create symbol view with pins placed per docs/sar_logic_pins.pdf (CLK, RST left; D[7:0] right as a bus; VDD top; VSS bottom), a 2×3-grid rectangle body and the instance label. Check and save with no warnings; instantiate it in ADC_LIB/top.
- Platforms
lin· Linux- Applications
- Cadence Virtuoso
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickgeom· Precise geometrytype· Text & forms- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 2 / 5
Proposed verifier
Read OA symbol: pins equal schematic terminals; sides per spec; bus notation D<7:0>; check-and-save log 0 warnings; top schematic instance present and netlists. SKILL disabled.
Proposed partial credit
40% pins and sides; 20% bus notation; 20% clean check; 20% instantiated
R07.04.01.01-T10 Run an LDO PVT corner sweep in ADE Assembler and report worst-case PSRR
Original instruction
For cell ldo_1v2 in fixtures/pmu_lib, open ADE Assembler, add tests for PSRR at 1 kHz and 1 MHz, and create corners tt/ss/ff × -40/27/125 °C × VDD 1.62/1.98 V. Run all 18 corners, add a spec PSRR@1kHz ≤ -50 dB, save the setup as psrr_corners, and record the worst corner and value in out/psrr.txt.
- Platforms
lin· Linux- Applications
- Cadence Virtuoso · Spectre
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clicktype· Text & formsnav· Pan/zoom/scroll- Work product
WP07· Simulation result- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
maestro view psrr_corners contains 2 tests and 18 corner points with given values and the spec; history run exists; grader reruns via ocean batch: worst corner and value in psrr.txt match within 0.5 dB. SKILL disabled.
Proposed partial credit
35% corner setup; 20% tests & spec; 20% run history present; 25% correct worst-case answer
R07.04.01.01-T11 Add metal fill to meet density windows in KLayout around keep-outs
Original instruction
fixtures/core_blk/core.gds fails density rules (met1-met3 must be 30-70% in every 100×100 µm window). In KLayout use the fill tool to add sky130 fill shapes on met1-met3 only outside the analog keep-out layer (KO, 999/0). Save core_filled.gds.
- Platforms
mac· macOSwin· Windowslin· Linux- Applications
- KLayout
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickgeom· Precise geometrynav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Density check script per window: all met1-met3 windows 30-70%; no fill overlapping KO; fill on dedicated fill datatype; DRC 0 new violations; LVS unchanged (fill floating). Macros disabled.
Proposed partial credit
50% windows in range (scaled); 25% KO respected; 25% DRC/LVS unchanged
R07.04.01.01-T12 Extract an inverter chain in Magic and compare post-layout delay to schematic
Original instruction
For fixtures/invchain/invchain.mag (5 stages, sky130), extract with Magic including R and C parasitics, write out/invchain_pex.spice, simulate a 1 GHz input in ngspice for both schematic and PEX netlists and report tpd (50%-50% A→Y) for each in out/delay.csv.
- Platforms
lin· Linux- Applications
- Magic · ngspice
- Interfaces
desk· Desktop GUIterm· Terminal- GUI need · task setting
HY· Hybrid- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickcode· Code & commands- Work product
WP07· Simulation result- Conditions
multiapp· Multi-app- Proposed difficulty
- 3 / 5
Proposed verifier
PEX netlist has R and C parasitics (count >0) and matches ports; grader reruns ngspice: reported delays within 5% of grader's values; PEX delay > schematic delay.
Proposed partial credit
35% correct extraction; 25% testbench runs; 40% delays within 5 percent
R07.04.01.01-T13 Clean a block's Calibre DRC with a waiver file and antenna-diode fixes
Original instruction
Calibre DRC on fixtures/rx_top (gpdk045) reports 7 results: 3 are approved waivers listed in docs/waivers.xlsx and 4 are antenna violations on gate nets. Create the Calibre waiver file for the 3, fix the 4 antenna errors in Virtuoso by adding diodes or metal jumpers, and rerun until 0 unwaived results. Keep LVS CORRECT.
- Platforms
lin· Linux- Applications
- Calibre · Cadence Virtuoso
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
vis· Visual judgmentgeom· Precise geometryclick· Point & click- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro appmultiapp· Multi-app- Proposed difficulty
- 5 / 5
Proposed verifier
Calibre DRC with waiver file: 0 unwaived; waivers match exactly the 3 listed (by rule and location); antenna ratios recomputed below limits; LVS CORRECT including any added diodes in netlist as allowed. SKILL disabled.
Proposed partial credit
25% waivers precise; 50% antenna violations fixed (12.5 pts each); 25% LVS still correct
R07.04.01.01-T14 Lay out a 5-stage ring oscillator in Virtuoso and hit frequency after PEX
Original instruction
Cell ro5 in fixtures/clk_lib (gpdk045) has a schematic oscillating at 3.2 GHz. Lay it out in Virtuoso with stages in a ring, equal inter-stage wire length, and a buffered output. Pass Calibre DRC/LVS, run Calibre xRC PEX, simulate the extracted view and keep post-layout frequency ≥2.8 GHz. Save layout and av_extracted.
- Platforms
lin· Linux- Applications
- Cadence Virtuoso · Calibre · Spectre
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
HY· Hybrid- Interaction primitives
geom· Precise geometrydrag· Drag & dropvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro applong· Long-horizon- Proposed difficulty
- 5 / 5
Proposed verifier
DRC 0; LVS CORRECT; extracted view exists; grader reruns Spectre on extracted view: f ≥2.8 GHz; inter-stage net lengths (from layout) within 10% of each other. SKILL disabled.
Proposed partial credit
20% layout complete; 20% DRC; 20% LVS; 40% PEX done & frequency target
R07.04.01.01-T15 Place sky130 PCell transistors in KLayout and wire them per a hand sketch
Original instruction
docs/nand2_sketch.png shows a NAND2 stick diagram. In KLayout, instantiate sky130 nfet/pfet PCells (W=0.65/1.0, L=0.15) from the library browser, place them per the sketch, and wire with li1/met1 including taps and pins A, B, Y, VPWR, VGND. Save nand2.gds and pass DRC and LVS against fixtures/nand2.spice.
- Platforms
mac· macOSwin· Windowslin· Linux- Applications
- KLayout
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
drag· Drag & dropgeom· Precise geometryvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
KLayout DRC 0; LVS match; PCell parameters equal spec; series NMOS and parallel PMOS orientation per sketch (device ordering by x-coordinate). Macros disabled.
Proposed partial credit
25% PCells with right params; 25% wiring; 25% DRC; 25% LVS
R07.04.01.01-T16 Control pair of T01: generate the sky130 inverter layout by script
Original instruction
Control pair of T01. Produce the same inverter (inv.gds, sky130, W/L as in fixtures/inv/inv.sch) using only scripts: Magic in batch Tcl mode or gdsfactory, plus netgen for LVS. No GUI is available. Save inv.gds and the script.
- Platforms
lin· Linux- Applications
- Magic · netgen · gdsfactory
- Interfaces
term· Terminal- GUI need · task setting
CL· CLI-sufficient- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
code· Code & commands- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 2 / 5
Proposed verifier
Same checks as T01: DRC 0, netgen LVS unique match, W/L and port labels. Script must reproduce inv.gds deterministically. Score compared against T01 to measure GUI vs script gap.
Proposed partial credit
30% devices with correct W/L; 30% DRC clean; 30% LVS match; 10% ports
R07.04.01.01-T17 Draw a StrongARM comparator in xschem with a testbench meeting decision time
Original instruction
In xschem create comparator.sch (StrongARM latch + SR latch, sky130, 1.8 V) with symbol comparator.sym and testbench tb_comp.sch: 1 GHz clock, differential input +1 mV around 0.9 V CM. Size devices so the output resolves (rail-to-rail 90%) within 200 ps of the clock edge at tt/27 °C. Save all schematics.
- Platforms
lin· Linuxmac· macOS- Applications
- xschem · ngspice
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
drag· Drag & dropclick· Point & clickvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader netlists and runs ngspice: decision time ≤200 ps for ±1 mV both polarities; correct output sign; topology graph matches StrongARM reference; symbol pins equal schematic ports. xschem Tcl console and --script disabled; .sch/.sym files written by any process other than xschem are flagged by a file audit log.
Proposed partial credit
35% topology; 15% symbol & testbench; 25% correct decisions; 25% timing
R07.04.01.01-T18 Fix check-and-save errors in a Virtuoso schematic until it netlists cleanly
Original instruction
Schematic fixtures/rf_lib/lna_core has 6 check-and-save problems (two floating nets, an output-to-output short, a pin without a wire, a mismatched bus width, an unnamed net crossing a page) and fails netlisting. Fix all in Virtuoso Schematic XL without changing intended topology (docs/lna_core_ref.pdf), then netlist with Spectre.
- Platforms
lin· Linux- Applications
- Cadence Virtuoso
- Interfaces
desk· Desktop GUI- GUI need · task setting
G3· GUI-only- GUI need · ordinary access
G2· GUI-essential- Interaction primitives
click· Point & clickdrag· Drag & dropvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
licensed· Licensed pro app- Proposed difficulty
- 3 / 5
Proposed verifier
si batch netlist succeeds; check-and-save 0 errors/0 warnings; netlist graph isomorphic to reference topology. SKILL disabled.
Proposed partial credit
60% six issues fixed (10 pts each); 40% netlist matches reference topology
R07.04.01.01-T19 Add guard rings and well taps to clear latch-up rules in a Magic layout
Original instruction
fixtures/lna_io/lna_io.mag (sky130) fails latch-up rules: n-well/p-sub taps farther than 15 µm from devices and no guard ring between the I/O NMOS and core PMOS. In Magic add taps and a double guard ring per docs/lu_rules.md, keeping DRC and LVS clean. Save the cell.
- Platforms
lin· Linuxmac· macOS- Applications
- Magic
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
geom· Precise geometryclick· Point & clickvis· Visual judgment- Work product
WP06· Code/engineering- Conditions
- None declared
- Proposed difficulty
- 3 / 5
Proposed verifier
Grader computes max device-to-tap distance ≤15 µm; double ring (N+ in nwell and P+) closed around I/O NMOS; Magic DRC 0; netgen LVS match. Sourcing Tcl script files is blocked in Magic; grader checks Magic's command log for interactive paint/box edits.
Proposed partial credit
35% tap distance rule; 35% guard ring; 15% DRC; 15% LVS
R07.04.01.01-T20 XOR two GDS revisions, document changes and revert an unintended met2 edit
Original instruction
Compare fixtures/pll/pll_rev3.gds with pll_rev4.gds in KLayout's XOR tool. List every changed layer and bounding box in out/xor_report.csv, then revert the one change on met2 that is not covered by docs/eco_rev4.txt, saving pll_rev4b.gds.
- Platforms
mac· macOSwin· Windowslin· Linux- Applications
- KLayout
- Interfaces
desk· Desktop GUI- GUI need · task setting
G2· GUI-essential- GUI need · ordinary access
CL· CLI-sufficient- Interaction primitives
click· Point & clickvis· Visual judgmentnav· Pan/zoom/scroll- Work product
WP06· Code/engineering- Conditions
hidden· Hidden/stale state- Proposed difficulty
- 3 / 5
Proposed verifier
xor_report.csv rows match grader XOR (layer, bbox within 0.5 µm; IoU ≥0.9); pll_rev4b XOR rev4 equals only the unintended met2 region; XOR rev3 equals only ECO-listed regions. KLayout Ruby/Python macros and -r batch mode disabled, and gdstk/gdspy absent from the VM, so the revert must be made in the layout editor.
Proposed partial credit
40% XOR report complete; 20% unintended change identified; 40% correct revert only
Mapped research references
Existing benchmark-to-class links from the research catalog. They are not record-level annotations, executions or product endorsements.