布局与板级约束
Placement & board constraints
Place components and define outline, keep-outs and rules to a mechanical spec.
20 条本项目编写的提案 · 分类 v1.1 · 新增基准运行 0 次。下方验证方式与部分得分规则是设计,不是执行结果。
- 典型应用
- KiCad PCB Editor · Altium · Allegro
- 小类 GUI 需求标签
G3· 仅 GUI
任务提案 · 20
展开查看完整原文与建议检查方式;两种界面均保留提案英文原文。
R07.03.02.01-T01 KiCad: board outline and M3 holes for an SN25 enclosure
原始指令
In KiCad 8 PCB Editor, open input/encabulator.kicad_pro, update PCB from schematic, draw an Edge.Cuts outline per input/sn25_enclosure.pdf (rounded rectangle with R2 corners), and place four M3 mounting holes (MountingHole_3.2mm_M3) on a 40.0 × 32.0 mm rectangle centred on the board.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
click· 指向与点击geom· 精确几何drag· 拖放- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 3 / 5
建议验证方式
Grader parses .kicad_pcb: closed Edge.Cuts loop matching enclosure outline (Hausdorff < 0.05 mm); 4 hole footprints at specified centres ±0.02 mm; all schematic footprints present. pcbnew scripting console and action plugins are disabled; file writes by non-KiCad processes are flagged.
建议部分得分
40% outline; 40% hole positions; 20% footprints imported.
R07.03.02.01-T02 KiCad: edge connectors with 1 mm overhang and decouplers near the MCU
原始指令
In input/node.kicad_pcb, place J1 (USB-C) and J2 (JST-PH) on the top board edge with exactly 1.0 mm overhang beyond Edge.Cuts, and place C1–C4 so each pad is within 5 mm of its assigned U1 power pin (per input/decap_map.csv), all on F.Cu with no courtyard overlaps.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
drag· 拖放geom· 精确几何click· 指向与点击- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 3 / 5
建议验证方式
Parsed board: connector body front edges 1.0 ±0.05 mm beyond Edge.Cuts; pad-to-pin distances ≤ 5 mm per map; kicad-cli pcb drc courtyard errors = 0. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
建议部分得分
40% connector overhang; 40% decoupler distances; 20% no courtyard overlaps.
R07.03.02.01-T03 KiCad: import enclosure DXF as outline with a 2 mm edge keep-out
原始指令
Import input/enclosure.dxf onto Edge.Cuts (mm units, origin at the DXF origin), make sure the outline is closed, add a rule area keeping out tracks, vias, pads and footprints within 2 mm of the edge, and move any footprint that violates it inward.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
click· 指向与点击drag· 拖放- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 2 / 5
建议验证方式
Edge.Cuts equals DXF geometry (Hausdorff < 0.01 mm); rule area polygon offset 2 mm inward with keep-out flags; DRC 0 rule-area violations; footprints otherwise unmoved where compliant. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
建议部分得分
40% outline import; 30% keep-out area; 30% violations cleared.
R07.03.02.01-T04 Altium: four identical channels placed with Room Copy Formats
原始指令
In input/adc4.PcbDoc, place channel 1 (room CH1) per input/ch1_placement.png, then replicate the placement to rooms CH2–CH4 with Copy Room Formats so all four channels have identical relative placement, arranged left to right at 18 mm pitch.
- 平台
win· Windows- 应用
- Altium Designer
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
G2· GUI 必要- 交互原语
drag· 拖放geom· 精确几何vis· 视觉判断- 工作产物
WP06· 代码 / 工程- 条件
licensed· 授权专业软件- 提案难度
- 4 / 5
建议验证方式
Grader exports pick-and-place: per-channel relative positions/rotations identical (±0.01 mm, 0°); room origins at 18.0 mm pitch; CH1 matches the reference image layout (component position error ≤ 0.5 mm). Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the board must be edited in the Altium GUI.
建议部分得分
30% CH1 placement; 50% replication exact; 20% pitch.
R07.03.02.01-T05 Allegro: Constraint Manager rules and a BGA region
原始指令
In Allegro PCB Editor, open input/fpga_board.brd and in Constraint Manager create physical/spacing classes per input/rules.xlsx (DDR, PWR, default) and a constraint region under the BGA (U1 courtyard) allowing 0.09 mm trace/space. Save.
- 平台
win· Windowslin· Linux- 应用
- Cadence Allegro
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
click· 指向与点击type· 文字与表单drag· 拖放- 工作产物
WP06· 代码 / 工程- 条件
licensed· 授权专业软件- 提案难度
- 4 / 5
建议验证方式
Grader exports constraints via Allegro batch (techfile export): classes and values match spreadsheet; region shape covers the BGA courtyard (IoU ≥ 0.95) with the specified region rules. SKILL loading, script replay and techfile import are disabled in the agent's Allegro environment and its VM has no shell, so rules must be set in Constraint Manager.
建议部分得分
50% class values; 30% region geometry; 20% net assignments to classes.
R07.03.02.01-T06 KiCad: ESP32 module antenna overhang and copper keep-out
原始指令
Place the ESP32-S3-WROOM-1 module in input/iot.kicad_pcb so its antenna overhangs the board edge per the Espressif guideline (antenna area outside the outline, or ≥ 15 mm keep-out), add a copper keep-out rule area under the antenna on all layers, and place power MOSFETs Q1–Q2 at least 20 mm from it.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
drag· 拖放geom· 精确几何click· 指向与点击- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 4 / 5
建议验证方式
Parsed board: antenna region polygon (from footprint) outside Edge.Cuts or fully in a no-copper rule area on all copper layers; Q1/Q2 courtyard distance ≥ 20 mm from antenna; DRC clean. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
建议部分得分
50% antenna placement rule; 30% keep-out area; 20% MOSFET distance.
R07.03.02.01-T07 Altium: board shape from an enclosure STEP with 3D height clearance
原始指令
Import input/case_lid.step as a 3D body in input/handheld.PcbDoc, define the board shape from the enclosure's PCB-seat face, and place components so none collides with the lid (3D clearance ≥ 0.5 mm, component height rule ≤ 8 mm under the dome region).
- 平台
win· Windows- 应用
- Altium Designer
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
G2· GUI 必要- 交互原语
drag· 拖放geom· 精确几何vis· 视觉判断- 工作产物
WP06· 代码 / 工程- 条件
licensed· 授权专业软件long· 长流程- 提案难度
- 5 / 5
建议验证方式
Grader exports board + components to STEP and runs collision against the lid: min clearance ≥ 0.5 mm; board outline matches seat face (Hausdorff < 0.05); height rule exists and DRC clean. Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the board must be edited in the Altium GUI.
建议部分得分
30% board shape; 50% no collisions; 20% height rule.
R07.03.02.01-T08 KiCad: decouplers within 2 mm of their pins on one side
原始指令
In input/fpga_break.kicad_pcb, place the 16 decoupling capacitors so each is within 2 mm of its assigned power pin (input/decap_map.csv), on B.Cu under the FPGA, rotated to minimise loop area (pads aligned to the pin-to-via direction), with zero courtyard overlaps.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
drag· 拖放geom· 精确几何- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 3 / 5
建议验证方式
Parsed board: all 16 caps on B.Cu; pad-to-pin distance ≤ 2 mm; courtyard DRC 0; orientation check ±15° vs reference direction. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
建议部分得分
50% distances; 20% layer; 20% no overlaps; 10% orientation.
R07.03.02.01-T09 Allegro: place and lock mechanical symbols at fixed coordinates
原始指令
In input/ctrl.brd, place mechanical symbols for 4 mounting holes, 2 fiducials and the board-to-board connector at the coordinates in input/mech.csv (relative to the board origin), set them to Fixed, and place the 3 tall capacitors within the height-restricted region rules.
- 平台
win· Windowslin· Linux- 应用
- Cadence Allegro
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
click· 指向与点击type· 文字与表单drag· 拖放- 工作产物
WP06· 代码 / 工程- 条件
licensed· 授权专业软件- 提案难度
- 3 / 5
建议验证方式
Grader extracts placement report: symbol positions ±0.01 mm, fixed property set; tall caps in allowed area; DRC (package height) clean. SKILL loading, script replay and techfile import are disabled in the agent's Allegro environment and its VM has no shell, so symbols must be placed interactively.
建议部分得分
50% mechanical placement; 20% fixed; 30% tall caps compliant.
R07.03.02.01-T10 KiCad: 4-layer stackup and net-class rules in Board Setup
原始指令
In input/motor.kicad_pcb Board Setup, define a 4-layer stackup per input/stackup.pdf (thicknesses, dielectric εr), net classes Power (0.5 mm track, 0.3 mm clearance), Default (0.2/0.2) and a differential pair class USB (0.2 mm width, 0.15 mm gap), and assign nets by pattern.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
click· 指向与点击type· 文字与表单- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 3 / 5
建议验证方式
Parsed .kicad_pcb/.kicad_pro: stackup layer thicknesses/εr exact; net classes and assignments (pattern-matched nets) exact. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
建议部分得分
40% stackup; 40% net classes; 20% assignments.
R07.03.02.01-T11 Fusion Electronics: round board in a Ø60 mm enclosure with angled connectors
原始指令
In Fusion Electronics, make the PCB for input/sensor_puck.fsch a Ø58 mm circle concentric with the Ø60 enclosure, with three M2.5 holes at 120° on a Ø50 PCD, connector J1 at 0° and J2 at 90° pointing radially outward at the edge.
- 平台
win· Windowsmac· macOS- 应用
- Fusion Electronics
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
geom· 精确几何drag· 拖放click· 指向与点击- 工作产物
WP06· 代码 / 工程- 条件
licensed· 授权专业软件- 提案难度
- 4 / 5
建议验证方式
Board export (.brd XML): circular outline Ø58 ±0.05; hole centres at radius 25 ±0.02 and 120° spacing; connector rotations 0°/90° ±0.5° with mating face at radius ≥ 28.5 mm. ULP and SCR script execution and Fusion's Scripts and Add-Ins are disabled for the agent, so the board must be laid out interactively.
建议部分得分
30% outline; 30% holes; 40% connector placement.
R07.03.02.01-T12 Altium: 2×3 embedded board array panel with rails and fiducials
原始指令
Create output/panel.PcbDoc in Altium with an Embedded Board Array of input/node.PcbDoc (2 × 3, 2 mm V-score spacing), 5 mm top/bottom rails, three panel fiducials and four tooling holes per input/panel_spec.pdf.
- 平台
win· Windows- 应用
- Altium Designer
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
click· 指向与点击type· 文字与表单geom· 精确几何- 工作产物
WP06· 代码 / 工程- 条件
licensed· 授权专业软件- 提案难度
- 3 / 5
建议验证方式
Grader reads panel document: array object with row/column counts and spacing exact; rail size; fiducial/tooling-hole positions ±0.05 mm. Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the board must be edited in the Altium GUI.
建议部分得分
40% array config; 20% rails; 40% fiducials and tooling holes.
R07.03.02.01-T13 KiCad: no-copper keep-outs around mounting holes
原始指令
In input/power.kicad_pcb, add rule areas forbidding tracks, vias and zones within 3 mm of each of the four mounting holes on all copper layers, refill zones, and fix any track that now violates the rule by moving it (not deleting nets).
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
click· 指向与点击drag· 拖放- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 2 / 5
建议验证方式
Rule areas: 4 circles r = 3 mm (+hole radius) at hole centres on all copper layers; DRC 0 violations and 0 unconnected; netlist connectivity unchanged. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
建议部分得分
40% rule areas; 40% violations fixed; 20% connectivity intact.
R07.03.02.01-T14 EasyEDA Pro: place 20 front-panel parts to a placement drawing
原始指令
In EasyEDA Pro (web), place the 20 LEDs, buttons and connectors of project 'FrontPanel' at the X/Y/rotation positions given in input/placement.pdf (dimensioned drawing, not a CSV), on the top layer.
- 平台
web· 任意系统(网页)- 应用
- EasyEDA Pro
- 交互表面
brow· 浏览器- GUI 需求 · 任务设定
G3· 仅 GUI- GUI 需求 · 普通权限
G2· GUI 必要- 交互原语
drag· 拖放geom· 精确几何vis· 视觉判断- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 3 / 5
建议验证方式
Grader exports pick-and-place CSV through the account: each part within ±0.05 mm and 0.5° of the drawing; score per part. Placement must be done in the editor (project history shows interactive moves; no CSV import). EasyEDA Pro extensions and API are disabled for the agent's account.
建议部分得分
Score = fraction of 20 parts within tolerance (90%); 10% layer correct.
R07.03.02.01-T15 KiCad: reduce ratsnest length by 30% while respecting constraints
原始指令
input/sensor.kicad_pcb has all 60 components dumped off-board. Place them inside the outline so total ratsnest length drops ≥ 30% vs the provided baseline placement value, while keeping connector positions fixed, decouplers ≤ 3 mm from pins and no courtyard overlaps.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
drag· 拖放geom· 精确几何vis· 视觉判断- 工作产物
WP06· 代码 / 工程- 条件
long· 长流程- 提案难度
- 4 / 5
建议验证方式
Grader computes minimum-spanning ratsnest length per net from the saved board; reduction ≥ 30% vs baseline (scaled credit); fixed connectors unmoved; decoupler distance and courtyard DRC checks. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
建议部分得分
50% ratsnest reduction (scaled); 20% decouplers; 20% no overlaps; 10% connectors fixed.
R07.03.02.01-T16 Altium: component clearance rule and BGA fanout keep-out
原始指令
In input/mcu.PcbDoc, add a Component Clearance rule (0.25 mm horizontal, 0.5 mm vertical), a placement room keeping other components ≥ 2 mm from the BGA for fanout escape, and move offending parts to satisfy both.
- 平台
win· Windows- 应用
- Altium Designer
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
G2· GUI 必要- 交互原语
click· 指向与点击type· 文字与表单drag· 拖放- 工作产物
WP06· 代码 / 工程- 条件
licensed· 授权专业软件- 提案难度
- 3 / 5
建议验证方式
Rules exported with exact values; grader's DRC report shows 0 component clearance and room violations; components moved minimally (mean displacement ≤ reference × 1.5). Altium's script engine (Run Script, script projects) is disabled for the agent and its VM has no shell, so the board must be edited in the Altium GUI.
建议部分得分
30% rules; 50% violations cleared; 20% minimal movement.
R07.03.02.01-T17 KiCad: align LEDs and buttons to front-panel cutouts
原始指令
Import input/front_panel.dxf on a User layer as a reference, then place D1–D8 and SW1–SW4 so their optical/actuator centres sit exactly at the DXF cutout centres (±0.1 mm), on F.Cu, and lock them.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
drag· 拖放geom· 精确几何click· 指向与点击- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 3 / 5
建议验证方式
Parsed board: each part's reference point (footprint origin offset per datasheet table) within 0.1 mm of the matching cutout centre; locked flag set; User layer contains the DXF. KiCad's scripting console and pcbnew Python module are removed, and a file-system audit log flags .kicad_pcb writes not made by the PCB Editor (hand-edited S-expressions fail).
建议部分得分
70% 12 parts aligned (≈5.8 each); 20% locked; 10% reference layer.
R07.03.02.01-T18 Allegro: replicate an 8-channel placement with module reuse
原始指令
In input/frontend.brd, place channel 1 per input/ch_layout.pdf, create a place-replicate module from it, and apply it to channels 2–8 in a 2 × 4 grid at 22 × 30 mm pitch, keeping net assignments correct per channel.
- 平台
win· Windowslin· Linux- 应用
- Cadence Allegro
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
drag· 拖放geom· 精确几何click· 指向与点击- 工作产物
WP06· 代码 / 工程- 条件
licensed· 授权专业软件long· 长流程- 提案难度
- 5 / 5
建议验证方式
Placement report: identical relative positions across 8 channels; grid pitch exact; each replicated component bound to the correct channel's nets (refdes mapping check). SKILL loading, script replay and techfile import are disabled in the agent's Allegro environment and its VM has no shell, so channels must be replicated interactively.
建议部分得分
25% channel 1; 50% replication; 25% grid and mapping.
R07.03.02.01-T19 KiCad: full 60-part placement under mechanical, thermal and EMI groups
原始指令
Place all components of input/drive.kicad_pcb according to input/placement_rules.md: mechanical (connectors and holes fixed), thermal (power stage near the heatsink edge, sensors ≥ 15 mm away), EMI (switching node loop < 40 mm², analog section separated by ≥ 5 mm from digital), plus courtyard DRC clean.
- 平台
win· Windowsmac· macOSlin· Linux- 应用
- KiCad PCB Editor
- 交互表面
desk· 桌面 GUI- GUI 需求 · 任务设定
G2· GUI 必要- GUI 需求 · 普通权限
CL· CLI 足够- 交互原语
drag· 拖放geom· 精确几何vis· 视觉判断- 工作产物
WP06· 代码 / 工程- 条件
long· 长流程- 提案难度
- 5 / 5
建议验证方式
Weighted scripted checks on the saved board (14 rules from placement_rules.md, loop area computed from placed part pad polygons); courtyard DRC 0. Score = weighted rules passed. The agent VM has no shell, text editor or Python, and KiCad's scripting console, action plugins and IPC API are disabled, so the board can only change by saving from the PCB Editor.
建议部分得分
Weighted rules: mechanical 25%, thermal 25%, EMI 30%, DRC 20%.
R07.03.02.01-T20 Control pair of T01: outline and holes via pcbnew Python
原始指令
Control pair of T01. Using KiCad's pcbnew Python API from a terminal (no GUI), add the same enclosure outline and four M3 holes to input/encabulator.kicad_pcb and save output/encabulator_py.kicad_pcb.
- 平台
lin· Linuxmac· macOSwin· Windows- 应用
- KiCad pcbnew API
- 交互表面
term· 终端api· API / SDK- GUI 需求 · 任务设定
CL· CLI 足够- GUI 需求 · 普通权限
AP· API 足够- 交互原语
code· 代码与命令- 工作产物
WP06· 代码 / 工程- 条件
- 未声明
- 提案难度
- 2 / 5
建议验证方式
Same outline and hole checks as T01; reported as the scripting baseline.
建议部分得分
50% outline; 50% hole positions.
已有研究映射
以下沿用研究目录中的基准与小类映射,不是逐题标注、执行记录或产品背书。