R07.04.01.03 · 任务小类

FPGA构建与时序收敛

FPGA build & timing closure

Assemble IP block designs, constraints and close timing in vendor tools.

20 条本项目编写的提案 · 分类 v1.1 · 新增基准运行 0 次。下方验证方式与部分得分规则是设计，不是执行结果。

典型应用: Vivado · Quartus Prime · Radiant
小类 GUI 需求标签: HY · 混合

任务提案 · 20

展开查看完整原文与建议检查方式；两种界面均保留提案英文原文。

R07.04.01.03-T01 Build a Zynq block design with AXI GPIO driving four LEDs and export the XSA

原始指令

In Vivado 2024.2 create project zynq_leds for the PYNQ-Z2 board (xc7z020clg400-1). In IP Integrator add the Zynq PS (board preset), an AXI GPIO (4-bit output, board interface leds_4bits), run connection automation, validate, create the HDL wrapper, generate the bitstream with WNS ≥0 and export hardware including bitstream to out/zynq_leds.xsa.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 drag · 拖放 type · 文字与表单
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 3 / 5

建议验证方式

Parse .bd JSON: processing_system7 + axi_gpio (C_GPIO_WIDTH=4, all outputs) connected via interconnect; address map assigned; validate_bd_design clean in batch; routed DCP timing WNS ≥0; XSA contains .bit and hwh. Journal checked for completion of all steps.

建议部分得分

35% block design correct; 15% validation clean; 30% bitstream with timing met; 20% XSA exported

R07.04.01.03-T02 Assign eight I/O with Pin Planner on a DE10-Lite and compile

原始指令

Open fixtures/de10_counter/de10_counter.qpf in Quartus Prime Lite 23.1. Using Pin Planner, assign CLOCK_50, KEY[1:0] and LEDR[4:0] to the pins in docs/DE10-Lite_manual.pdf (table 3-x) with 3.3-V LVTTL standard. Compile and save.

平台: win · Windows lin · Linux
应用: Quartus Prime
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 type · 文字与表单 drag · 拖放
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 2 / 5

建议验证方式

.qsf contains exactly 8 location assignments matching the key and IO_STANDARD 3.3-V LVTTL for each; no extra pin assignments; compile succeeds (fit report shows those pins).

建议部分得分

60% correct pin locations (7.5 pts each); 20% IO standards; 20% compile success

R07.04.01.03-T03 Constrain a 200 MHz clock and pipeline the critical path until timing closes

原始指令

fixtures/mac_unit (Vivado, xc7a100t) fails at 200 MHz with WNS -1.9 ns through a 32×32 multiply-add. Add a 5.0 ns create_clock in constraints.xdc, then pipeline the RTL (add ≤3 register stages, use DSP48 MREG/PREG) keeping the cycle-accurate behavior described by the new latency in docs/spec.md. Implement with WNS ≥0 and pass the provided testbench.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI term · 终端
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: code · 代码与命令 click · 指向与点击 vis · 视觉判断
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 4 / 5

建议验证方式

Grader implements with its golden XDC (5.0 ns): WNS ≥0, WHS ≥0; testbench with expected latency passes in xsim; DSP48 utilization uses internal pipeline registers; ≤3 added stages.

建议部分得分

10% clock constrained; 40% timing met; 35% testbench passes; 15% DSP pipelining used

R07.04.01.03-T04 Clear CDC critical warnings with XPM synchronizers and datapath constraints

原始指令

fixtures/cam_bridge (Vivado, xczu3eg) has 3 clock domains; report_cdc shows 14 Critical (CDC-1, CDC-4, CDC-10). Insert xpm_cdc_single / xpm_cdc_gray / xpm_cdc_handshake as appropriate in RTL, add set_max_delay -datapath_only only where justified, and get report_cdc to 0 Critical with timing met. Explain each fix in out/cdc_fixes.md.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI term · 终端
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: code · 代码与命令 vis · 视觉判断 click · 指向与点击
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 4 / 5

建议验证方式

Grader reruns synth/impl: report_cdc 0 Critical; no blanket set_false_path between clocks; max_delay only on XPM-internal paths; WNS/WHS ≥0; existing testbench still passes.

建议部分得分

45% CDC criticals cleared (scaled); 20% no blanket false paths; 20% timing; 15% testbench

R07.04.01.03-T05 Configure an MMCM with three output clocks via Clocking Wizard

原始指令

In fixtures/eth_cam (Vivado, Arty A7-100) add a Clocking Wizard IP: 100 MHz input, outputs 125 MHz, 200 MHz and 25 MHz (0° phase), reset active-low, locked output. Instantiate it in top.v, drive the three existing clock domains from it, regenerate output products and implement with timing met.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 type · 文字与表单
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 3 / 5

建议验证方式

.xci parameters: CLKOUT1/2/3 requested and actual frequencies 125/200/25 MHz ±0.1%; RESET_TYPE ACTIVE_LOW; LOCKED enabled; netlist clocks of the 3 domains driven by MMCM outputs; WNS/WHS ≥0.

建议部分得分

40% IP configuration; 30% instantiated & wired; 30% timing met

R07.04.01.03-T06 Assemble a Nios V system in Platform Designer and simulate a boot

原始指令

In Quartus Prime Lite 23.1 for MAX 10 (10M50DAF484C7G), create Platform Designer system soc.qsys: Nios V/m, 64 KB on-chip RAM initialised from fixtures/hello.hex, JTAG UART, 8-bit PIO output. Assign base addresses without overlap, generate HDL and a simulation model, compile, and run the provided Questa testbench showing PIO = 0xA5.

平台: win · Windows lin · Linux
应用: Quartus Prime · Questa
交互表面: desk · 桌面 GUI term · 终端
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 drag · 拖放 type · 文字与表单
工作产物: WP06 · 代码 / 工程
条件: multiapp · 多应用
提案难度: 4 / 5

建议验证方式

Parse .qsys: 4 components with stated params and connections; no address overlaps; RAM init file set; compile succeeds; grader runs testbench: PIO output 0xA5 within 200 µs sim time.

建议部分得分

35% system composed; 15% addresses; 20% compile; 30% simulation shows 0xA5

R07.04.01.03-T07 Constrain pins and a 48 MHz clock in Lattice Radiant and build a bitstream

原始指令

Open fixtures/ice_blink/ice_blink.rdf in Lattice Radiant 2024.1 for iCE40UP5K-SG48. Using the Device Constraint Editor assign clk to pin 35, led_r/g/b to pins 39/40/41 (LVCMOS33), add a 48 MHz create_clock in the PDC, and export the bitstream.

平台: win · Windows lin · Linux
应用: Radiant
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 type · 文字与表单
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 2 / 5

建议验证方式

PDC contains 4 ldc_set_location entries and IO_TYPE LVCMOS33; create_clock period 20.833 ns; bitstream .bin exists; timing report shows constraint met.

建议部分得分

50% pin locations; 20% IO type; 15% clock constraint; 15% bitstream

R07.04.01.03-T08 Insert an ILA on three nets with a trigger and generate debug probes

原始指令

In fixtures/spi_master (Vivado, Basys 3) synthesize, open Set Up Debug, mark sclk, mosi and state[3:0] for debug, create an ILA with depth 4096 and input pipe stages 1 on clk_100, implement and write the bitstream and debug probes file. Save a trigger setup (state == 4'h3 rising) as out/trigger.tas.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: G2 · GUI 必要
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 nav · 平移 / 缩放 / 滚动 type · 文字与表单
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 3 / 5

建议验证方式

Routed DCP contains ila core with depth 4096 and probe widths 1,1,4 connected to the named nets; .ltx lists those probes; trigger file condition state==3; timing met. XDC-based debug (manual create_debug_core lines) flagged by journal.

建议部分得分

40% ILA with correct probes; 15% depth/pipe; 25% bitstream + ltx; 20% trigger setup

R07.04.01.03-T09 Set up a DFX partial-reconfiguration design with two RMs and partial bitstreams

原始指令

fixtures/dfx_filters (Vivado, ZCU102) contains a static design and two filter modules (lpf, hpf) for region rp_filter. Enable Dynamic Function eXchange, create the partition definition, draw a Pblock for the RP sized to ≤1.3× resources, define two configurations, implement both and generate full and partial bitstreams. pr_verify must pass.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 geom · 精确几何 nav · 平移 / 缩放 / 滚动
工作产物: WP06 · 代码 / 工程
条件: licensed · 授权专业软件 long · 长流程
提案难度: 5 / 5

建议验证方式

Project has partition def with 2 RMs and 2 configurations; Pblock contains RP with SNAPPING_MODE on and utilization 1/1.3-1 of capacity; both runs WNS ≥0; pr_verify PASS; 2 partial .bit files plus full.

建议部分得分

20% DFX partition set; 25% Pblock sized/placed; 25% both configs implemented; 30% pr_verify & partial bitstreams

R07.04.01.03-T10 Close -0.6 ns timing with strategies, floorplanning and phys_opt only

原始指令

fixtures/video_scaler (Vivado, xc7k325t) misses 6.4 ns timing (WNS -0.6 ns). Without changing RTL or the clock, close timing using implementation strategies, Pblocks, phys_opt_design and justified multicycle paths only from docs/allowed_mcp.txt. Write the final checkpoint and a log of attempts in out/closure.md.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI term · 终端
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: vis · 视觉判断 geom · 精确几何 code · 代码与命令
工作产物: WP06 · 代码 / 工程
条件: licensed · 授权专业软件 long · 长流程
提案难度: 5 / 5

建议验证方式

Grader re-times final DCP with golden XDC plus allowed MCPs only: WNS ≥0, WHS ≥0; RTL hash unchanged; any constraint not in allowed list invalidates; route_status 100%.

建议部分得分

60% WNS improvement scaled from -0.6 to 0; 15% hold met; 15% constraints legal; 10% closure log

R07.04.01.03-T11 Write SDC with PLL-derived clocks and IO constraints in Quartus Timing Analyzer

原始指令

fixtures/adc_capture (Quartus, Cyclone V) uses a PLL generating 3 clocks and a source-synchronous ADC input. Write adc_capture.sdc: base 50 MHz clock, derive_pll_clocks, a virtual ADC clock, set_input_delay min/max from docs/adc_timing.pdf, and false paths for the async reset. Timing Analyzer must report no unconstrained paths and positive slack.

平台: win · Windows lin · Linux
应用: Quartus Prime
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: type · 文字与表单 click · 指向与点击 vis · 视觉判断
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 3 / 5

建议验证方式

quartus_sta batch: report_ucp empty; all setup/hold slacks ≥0; input delay values equal datasheet-derived key ±0.05 ns; virtual clock exists.

建议部分得分

25% clocks; 35% IO delays correct; 20% no unconstrained; 20% slack ≥0

R07.04.01.03-T12 Add a Signal Tap instance with a sequential trigger in Quartus

原始指令

In fixtures/i2c_ctrl (Quartus Lite, DE10-Lite) create Signal Tap file stp1.stp: sample clock clk, nodes scl, sda, state[2:0], depth 4096, sequential trigger: state==3'd2 then sda falling. Enable it in the project, compile and confirm the .sof contains the instance.

平台: win · Windows lin · Linux
应用: Quartus Prime
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: G2 · GUI 必要
GUI 需求 · 普通权限: G2 · GUI 必要
交互原语: click · 指向与点击 drag · 拖放 type · 文字与表单
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 3 / 5

建议验证方式

Parse .stp XML: nodes and depth correct; trigger flow sequential with 2 stages as specified; .qsf references stp1.stp with ENABLE_SIGNALTAP ON; compile report lists Signal Tap instance. Quartus Tcl console and quartus_sh/quartus_stp scripting disabled; stp1.stp must be saved by the Signal Tap GUI, and writes to .stp/.qsf by other processes are flagged by a file audit log.

建议部分得分

35% nodes; 15% depth; 30% trigger sequence; 20% compiled in

R07.04.01.03-T13 Build an HLS FIR kernel at II=1 and integrate it into a Zynq block design

原始指令

Implement a 32-tap FIR (coefficients fixtures/fir_coefs.txt, 16-bit fixed point) in Vitis HLS with AXI4-Stream in/out and AXI-Lite control at II=1, 200 MHz. Pass C/RTL cosimulation, export IP, add it to the block design in fixtures/zu_dma (Vivado, Ultra96-V2) between DMA MM2S/S2MM, and implement with timing met.

平台: win · Windows lin · Linux
应用: Vivado · Vitis HLS
交互表面: desk · 桌面 GUI term · 终端
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: code · 代码与命令 click · 指向与点击 drag · 拖放
工作产物: WP06 · 代码 / 工程
条件: multiapp · 多应用 long · 长流程
提案难度: 5 / 5

建议验证方式

HLS report: II=1, achieved clock ≤5 ns; cosim PASS with golden vectors; block design contains IP connected in DMA loop; validate clean; implementation WNS ≥0; grader runs PS-side xsim/QEMU test vectors match within 1 LSB.

建议部分得分

25% HLS II=1 & timing; 20% cosim; 25% integration; 30% implementation timing & vector match

R07.04.01.03-T14 Build an AXI DMA loopback block design with a correct address map

原始指令

In Vivado for ZCU104 create a block design: Zynq UltraScale+ MPSoC (board preset), AXI DMA (no SG, 26-bit length), AXI4-Stream Data FIFO looping MM2S to S2MM, interrupts concatenated to pl_ps_irq0, HP0 port for data. Assign the address map, validate, generate bitstream with timing met, export XSA.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 drag · 拖放 nav · 平移 / 缩放 / 滚动
工作产物: WP06 · 代码 / 工程
条件: licensed · 授权专业软件
提案难度: 4 / 5

建议验证方式

.bd JSON: DMA params match; FIFO in loop; IRQs concatenated; DMA masters mapped to HP0 DDR range; validate clean; WNS ≥0; XSA exported.

建议部分得分

35% topology; 35% address map & IRQs; 20% timing; 10% XSA

R07.04.01.03-T15 Migrate a Cyclone IV design to Cyclone V and replace legacy PLL IP

原始指令

fixtures/legacy_vga targets EP4CE22 with an ALTPLL. Retarget the project to 5CSEMA5F31C6 (DE1-SoC), replace ALTPLL with an Altera PLL IP keeping 25.175 MHz and 50 MHz outputs, regenerate IP, remap pins per docs/DE1-SoC_pins.csv, and compile with timing met.

平台: win · Windows lin · Linux
应用: Quartus Prime
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 type · 文字与表单 multi · 跨应用
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 4 / 5

建议验证方式

.qsf device 5CSEMA5F31C6; new PLL IP outputs 25.175±0.01 MHz and 50 MHz; no ALTPLL instances; pins equal CSV mapping; compile succeeds; quartus_sta slack ≥0.

建议部分得分

20% device retargeted; 30% PLL replaced correctly; 25% pins remapped; 25% compile & timing

R07.04.01.03-T16 Write a non-project-mode Vivado Tcl build script for an Arty A7 design

原始指令

For fixtures/uart_echo (RTL + arty.xdc), write build.tcl for Vivado non-project batch mode: read sources, synth_design for xc7a35ticsg324-1L, opt/place/route, write_bitstream to out/uart_echo.bit, and write timing/utilization reports. Run it with vivado -mode batch.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: term · 终端
GUI 需求 · 任务设定: CL · CLI 足够
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: code · 代码与命令
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 2 / 5

建议验证方式

Grader runs build.tcl in a clean dir: bitstream produced; part correct; timing summary WNS ≥0; reports exist; no project (.xpr) created.

建议部分得分

40% script runs to bitstream; 30% timing met; 30% reports

R07.04.01.03-T17 Plan LVDS ADC I/O in a single bank with correct standards and termination

原始指令

fixtures/adc_lvds (Vivado, xc7k160t) needs a 14-bit DDR LVDS ADC (DCO, FCO, D0-D6 pairs). In the I/O Planning view assign all pairs to bank 16 using clock-capable pins for DCO/FCO, set IOSTANDARD LVDS_25 with DIFF_TERM TRUE, and keep VCCO consistent. Run report_drc and DRC must be clean for IO rules.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: G2 · GUI 必要
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: drag · 拖放 click · 指向与点击 vis · 视觉判断
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 3 / 5

建议验证方式

XDC: 9 differential pairs in bank 16; DCO/FCO on MRCC/SRCC P-side pins; LVDS_25 + DIFF_TERM TRUE; report_drc no IO errors; implementation succeeds. Vivado Tcl console and -mode batch/tcl disabled; pin constraints must appear in vivado.jou as I/O Planning view actions, and XDC writes by other processes are flagged by a file audit log.

建议部分得分

40% pairs in bank 16 legal; 20% clock-capable pins; 25% IO standards; 15% DRC/impl clean

R07.04.01.03-T18 Cut dynamic power by 15% using activity data and power-optimization options

原始指令

fixtures/fft_engine (Vivado, xc7a200t) has a SAIF activity file sim/fft.saif. Run report_power with it, then reduce dynamic power by ≥15% via power_opt_design, BRAM enable gating in RTL, or clock enables, without breaking timing or the testbench. Save before/after power reports to out/.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI term · 终端
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: code · 代码与命令 vis · 视觉判断 click · 指向与点击
工作产物: WP07 · 仿真结果
条件: 未声明
提案难度: 3 / 5

建议验证方式

Grader recomputes report_power with the SAIF on final DCP: dynamic power ≤0.85× baseline; WNS ≥0; testbench passes; reports present.

建议部分得分

15% baseline with SAIF; 50% reduction (scaled to target); 20% timing; 15% testbench

R07.04.01.03-T19 Generate a PLL module in Radiant IP Catalog for 48 MHz from 12 MHz

原始指令

In fixtures/usb_dev (Lattice Radiant, iCE40UP5K) use IP Catalog to create pll48 (input 12 MHz, output 48 MHz, global buffer), instantiate it in top.v replacing the external 48 MHz input, update the PDC clock constraints, and build a bitstream with timing met.

平台: win · Windows lin · Linux
应用: Radiant
交互表面: desk · 桌面 GUI
GUI 需求 · 任务设定: HY · 混合
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: click · 指向与点击 type · 文字与表单 code · 代码与命令
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 3 / 5

建议验证方式

IP .ipx config: in 12 MHz, out 48 MHz achieved exactly; top uses pll48 output; PDC clock on PLL output; timing report met; bitstream exists.

建议部分得分

40% PLL configured; 25% instantiated; 15% constraints; 20% bitstream timing met

R07.04.01.03-T20 Rebuild with incremental implementation after a small RTL change

原始指令

fixtures/pcie_bridge (Vivado) has a timing-closed routed reference checkpoint ref/routed.dcp. Apply the RTL patch in patches/fix_status_reg.diff, then run incremental implementation against the reference so that ≥95% of cells are reused and timing stays met. Save the new routed DCP and the incremental reuse report.

平台: win · Windows lin · Linux
应用: Vivado
交互表面: desk · 桌面 GUI term · 终端
GUI 需求 · 任务设定: CL · CLI 足够
GUI 需求 · 普通权限: CL · CLI 足够
交互原语: code · 代码与命令
工作产物: WP06 · 代码 / 工程
条件: 未声明
提案难度: 3 / 5

建议验证方式

report_incremental_reuse: cell reuse ≥95%; patch applied (RTL hash); WNS/WHS ≥0; routed DCP present.

FPGA构建与时序收敛

任务提案 · 20

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原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

原始指令

建议验证方式

建议部分得分

已有研究映射

同工作流族的小类